DDC Chain Architecture

Digital Down-conversion Chain Implementation on AI Engine (XAPP1351)

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1.0 English

This section explains the architecture of the DDC chain and how it works. The input to the DDC chain is a composite signal comprising of one or more radio or intermediate frequency (RF or IF) carriers and the output is one or more carriers at the baseband sample rate for further processing. The following procedures are performed in the DDC chain.

  1. Mixing to shift the signal spectrum from the selected carrier frequencies to the baseband frequency.
  2. Decimation to reduce the sample rate.
  3. Filtering to remove adjacent channels, minimize aliasing, and maximize the received signal-to-noise ratio (SNR).

An example architecture for a DDC chain is shown in the following figure. An analog-to-digital converter (ADC) samples the analog signal and feeds it into the DDC processing chain. Optionally, there is an initial frequency translation (to shift the center frequency from passband to baseband), RF processing, and additional filters (decimation) that can be performed prior to the DDC function, shown in the following figure as the Digital RF Processing block.

This application note covers the functions of the main mixer and filters shown in the Digital Down Converter block in the following figure. The half band filter (HBF47) decimates the input signal by two. If it is a 4G five carrier (5c) LTE 20 MHz signal, then five channels are extracted by mixers with selected carrier frequencies and followed by a filter chain (HBF11/HBF23/FIR89) to reduce the sample rate to 30.72 MSPS. If it is a 5G NR one carrier (1c) 100 MHz signal, then the signal coming from the mixer goes to FIR199 directly. Because 5G NR has a much narrower transition band than that of LTE, the 5G NR channel filter has longer taps. In this case study, a channel filter with 199 taps is employed for the 5G NR 100 MHz carrier.

Figure 1. DDC Block Diagram Example