Digital Down-conversion Chain Implementation on AI Engine (XAPP1351)

Document ID
Release Date
1.0 English

The DDC chain is a key component in wireless communication systems. It is part of the receive path that links the baseband processing and radio front end. A DDC performs down-conversion on the input signal to the baseband sample rate. For instance, in a 100 MHz 5G New Radio (NR) system the sample rate of the radio front end is 245.76 Mega samples per second (MSPS), whereas the nominal sample rate of the baseband signal is 122.88 MSPS. For these cases, sample rate conversion from 245.76 MSPS to 122.88 MSPS must be performed in the DDC. Furthermore, 5G NR signals have a narrow transition band which calls for a long channel filter to offer good passband flatness and steep stop band attenuation. The following figure shows a typical DDC implementation for a 100 MHz 5G NR system which can support 5G NR or Long-Term-Evolution (LTE) carriers. Because the nominal sample rates of 20 MHz LTE and 100 MHz 5G NR carriers differ by a factor of four, two filter chains have to be instantiated as shown in the following figure.

Figure 1. DDC Implementation for 5G NR and 4G LTE

The Versal AI Core series has an array of AI Engines that are optimized for wireless radio applications supporting multiple numerologies and carrier configurations. The array consists of a number of AI Engines, each comprising a 32-bit scalar RISC processor, fixed and floating-point vector units, data memory, and interconnect. In each AI Engine the vector unit is capable of 32 real-by-real 16-bit MAC operations in one 1 GHz+ clock cycle, and memory load and store units that can read 512 bits data from and write 256 bits into local memory every clock cycle. There are hundreds of such AI Engines in one single chip that are suitable for compute-intensive applications such as wireless radio.

Figure 2. Block Diagram of One AI Engine Tile

This application note provides a method to design a flexible, scalable, and resource-efficient filter chain that runs on AI Engine in Versal AI Core devices. It also shows advanced techniques for mapping complex functions to the AI Engine array by leveraging the unique architecture of Versal devices for high performance and efficiency. This application note uses digital down-conversion as an example for illustration purpose, but this methodology is applicable to a wide range of applications including but not limited to wireless signal processing.