Using the Hard Block Planner Window - 2023.2 English

Vivado Design Suite User Guide: Using the Vivado IDE (UG893)

Document ID
UG893
Release Date
2023-10-25
Version
2023.2 English

The Hard Block Planner window allows you to place the hard blocks within a device, and provides a visual feedback in the Device window for assigning the location of the REFCLK pins, the GT_QUADs, and the Hard-IP blocks. Once you open the synthesized design, it reads and processes the netlist objects and collects all hard IPs available in a design. The Hard Block Planner window groups GT_QUADs under Hard-IPs, such as PCIe and DCMAC. It also lists the soft IPs and standalone GTs in the design under a separate drop-down menu, alongside the hard IPs, to facilitate the planning of GT blocks. This planner allows you to cross-probe the location in the Device window view for changing or assigning the site.

Figure 1. Hard Block Planner Window

To view the Hard Block Planner window, open Synthesized/Implemented design. The Hard Block Planner window opens by default after opening Synthesized/Implemented design. Alternately, it can be opened from the Windows menu.

Tip: By default the Hard Block Planner does not process netlist objects after opening the Synthesized/Implemented design. Click Populate Hard Block Planner data in the Hard Block Planner Window to process netlist objects and populate the data.

Hard Block Planner Window Columns

The Hard Block Planner window has the following columns:
Name
Specifies the instance name of the hard block.
Library Cell
Provides the library name of the hard block.
Site
Provides the location of the library cell instance.
Fixed
Specifies whether the BEL location is fixed or not.
Clock Region
Specifies the clock region.
Bank
Specifies the bank.
REFCLK Source
Provides the clock name of the reference clock.

Hard Block Planner Window Tool Bar Commands

The local tool bar contains the following commands:
Search
Opens the search bar to allow you to quickly locate objects in the Hard Block Planner window.
Collapse All
Collapses all hierarchical tree objects to display only the top-level objects.
Expand All
Expands all hierarchical tree objects to display all elements of the Hard Block Planner window.
Schematic
Creates a schematic from the selected objects.
Show Hard-IP Connectivity
Selects and displays all GTs and IPs of the design on the Device window.
Show Hard-IP Connectivity for selected IP groups
Selects and displays all GTs and IPs of the design on the Device window for the selected IP Group.
Hide Hard-IP Connectivity
Deselects all GTs and IPs of the design on the Device window.
Note: For more information on using the Hard Block Planner, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).