GPIO Reset to PL - 2025.1 English - UG1137

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

Document ID
UG1137
Release Date
2025-06-25
Version
2025.1 English

Vivado configuration allows you to enable fabric resets from PS to PL. The following figure shows that the Zynq UltraScale+ block outputs pl_resetn0 and pl_resetn1 signals with Fabric Reset Enabled and the Number of Fabric Resets set to 2, can be used to drive reset pins of PL components.

Figure 1. Resets from PS to PL

The pl_resetn signals, implemented with PS GPIOs, are released after bitstream configuration in software using the psu_ps_pl_reset_config_data function. In cases where a subsystem also uses GPIO for purposes other than reset, the GPIO block is included in the subsystem definition. The following figure illustrates an example of an APU subsystem with GPIO configured as a slave peripheral.

Figure 2. APU Subsystem with GPIO

In cases where GPIO is a subsystem slave peripheral, the entire GPIO component resets as part of the restart process when the subsystem is restarted. Because pl_resetn is implemented with GPIOs, pl_resetn is forced low during the subsystem restart. This behavior can be undesirable if the pl_resetn signals are used to drive PL IPs in subsystems other than the one being reset. For example, if pl_resetn0 drives resets for PL IPs in the APU subsystem and pl_resetn1 drives PL IPs for the RPU subsystem, during an APU subsystem restart, both pl_resetn0 and pl_resetn1 are forced into the reset state.

Consequently, the PL IPs in the RPU subsystem also reset. This behavior is incorrect because an APU restart should not affect the RPU subsystem, given that GPIO is implicitly shared between the APU and RPU subsystems via the pl_resetn signals. Because sharing of peripherals is not supported for subsystem resets, pl_resetn causes issues during subsystem resets. The workaround is to skip idling and resetting the GPIO peripheral during any subsystem restart, even if the component is assigned in the subsystem/isolation configuration.

To skip the GPIO reset during the node idling and reset, build the PMU firmware with the following flag: REMOVE_GPIO_FROM_NODE_RESET_INFO.

Note: The GPIO component also goes through a reset cycle during a PS-only reset. The PMU firmware enables PS-PL isolation prior to executing the PS-only reset, which locks pl_resetn to High. However, as soon as the FSBL removes the PS-PL isolation, the reset state goes Low. The FSBL then calls psu_ps_pl_reset_config_data to reconfigure pl_resetn back to High. This reconfiguration is necessary because resetting the PL components ensures proper synchronization of software and hardware states after the reset.