The Embedded Memory Generator pipelines the en[a|b] input internally to drive memories and registers at each
pipeline stage. For pipelined designs that do not tie en[a|b] High, this
results in a power savings with respect to the Embedded Memory Generator (EMG) IP, which
applies en[a|b] to all resources in parallel and therefore
enables memories for the duration of the pipeline depth.
The sleep port and WAKEUP_TIME parameters are used in
conjunction to implement various sleep modes on the underlying memory primitives. When
WAKEUP_TIME is 0, the sleep input is unused. A WAKEUP_TIME
value of 2 implies a two clock cycle wakeup period, and therefore either the BRAM
SLEEP port or URAM SLEEP port function.
You are responsible for complying with relevant signaling requirements to avoid data corruption or uncertainty.
When CLOCKING_MODE is 0, the sleep input port is pipelined
such that it is applied to synchronous elements in alignment with their pipeline stage,
synchronous to clka. You will continue to receive valid read
outputs for WAKEUP_TIME
clka cycles after sleep is asserted, and must wait for
READ_LATENCY_[A|B] + WAKEUP_TIME
clka clock cycles following the synchronous removal of sleep
until the corresponding dout[a|b] values are again valid.
When CLOCKING_MODE is 1, the sleep input port is not
pipelined such that it is applied asynchronously to all elements in parallel. As such, the
user will begin to receive invalid read outputs immediately, and must wait for READ_LATENCY_[A|B] + WAKEUP_TIME clk[a|b] clock cycles following
the asynchronous removal of sleep until the corresponding dout[a|b] values are again valid.