Constraining the Core - 1.0 English

Embedded Memory Generator LogiCORE IP Product Guide (PG326)

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1.0 English

Following are the constraints associated with this core:

Clock Constraints

create_clock -period 20.0 -name aclk [get_ports clka]

Following constraint is applicable only for dual-port memories.

create_clock -period 20.0 -name bclk [get_ports clkb]

Other Constraints

set_false_path constraint is needed for the independent clock distributed RAM based memory if the design takes care of avoiding address collision (write address != read address at any given point of time). Set USE_EMBEDDED_CONSTRAINT = 1 if IP needs to take care of necessary constraints.