The Embedded Memory Generator core supports the
use of built-in Hamming ECC mode (both ECC encoding and decoding enabled for all
utilized write and read ports, respectively), encode-only ECC mode (ECC encoding enabled
for all utilized write ports), and decode-only ECC mode (ECC decoding enabled for all
utilized read ports), for block RAM and UltraRAM mapping by utilizing the built-in ECC
functionality of those memory primitives. The various ECC modes are enabled by changing
the parameter ECC_MODE from its default of 0 (disable) to 1 (encode
only), 2 (decode only), or 3 (encode and decode). When both encoding and decoding are
enabled, each write operation generates eight protection bits for every 64 bits of data,
which are stored with the data in memory. These bits are used during each read operation
to correct any single-bit error, or to detect (but not correct) any double-bit
error.
The write and read widths must be multiple of 64 bits for both encode and decode mode.
When encode only mode is enabled, each write operation generates eight protection bits for every 64 bits of data which are stored with the data in memory. The read data directly come to the core output. In this case the write widths must be multiple of 64 and read widths must be multiple of 72.
When decode only mode is enabled, write width must be a multiple of 72 bits as you must provide the encoded information along with actual data which are stored in the memory. The decoding is done on the memory read data. In this case the write widths must be a multiple of 72 and read widths must be a multiple of 64.
This operation is transparent for you. Two status outputs
(sbiterr
and dbiterr) indicate the three possible read results: no error, single error
corrected, and double error detected. For single-bit errors, the Read operation does not
correct the error in the memory array; it only presents corrected data on dout.
Error Injection
The Embedded Memory Generator core supports
error injection through two optional pins: injectsbiterr and injectdbiterr. You
can use these optional error injection pins as debug pins to inject single or
double-bit errors into specific locations during write operations. You can then
check the assertion of the sbiterr and dbiterr signals at the output of those addresses. You
have the option to have no error injection pins, or to have only one or both of the
error injection pins.
The two error injection ports, and the two error output ports are
optional and become available only when the ECC option is chosen. If you have not
selected the ECC feature, the primitive's injectsbiterr and injectdbiterr ports
are internally driven to '0', and the primitive's outputs sbiterr and dbiterr are not connected
externally.
The following figure shows the assertion of the sbiterr and dbiterr
output signals when errors are injected through the error injection pins during a
write operation.
When the injectsbiterr and injectdbiterr inputs are asserted together at the same
time for the same address during a write operation (as in the case of address 3 in
the above figure), the injectdbiterr input takes
precedence, and only the dbiterr output is asserted
for that address during a read operation. The data output for this address is not
corrected.