The Embedded Memory Generator core allows optional output registers, which might improve the performance of the core. You might choose to include register stages at two places: at the output of the block RAM/UltraRAM primitives and at the output of the core.
Registers at the output of the block RAM/UltraRAM primitives reduce the impact of the clock-to-out delay of the primitives. Registers at the output of the core isolate the delay through the output multiplexers, improving the clock-to-out delay of the Embedded Memory Generator core. Each optional register stage used adds an additional clock cycle of latency to the read operation.
The Register Port [A|B] Output of Memory Primitives option might be implemented using the embedded block RAM/UltraRAM registers, requiring no further device resources. All other register stages are implemented in device general interconnect. The following figure shows an example of memory that has been configured using both output register stages for one of the ports.
Optional Pipeline Stages
