Embedded Memory Generator Basic Options Tab - 1.0 English - PG326

The main Embedded Memory Generator tab is used to define the interface options and block RAM port options for the core.

Figure 1. Embedded Memory Generator Basic Options Tab

Operating Mode

The mode in which the Embedded Memory Generator core is used in the IP integrator. There are two modes available when using IP integrator, and the default is memory controller.

Memory Controller Mode

Select this mode if you are using AXI block RAM Controller (axi_bram_ctrl ) or a Local Memory Bus Interface controller(lmb_bram_if_ctrl). All port parameters are greyed out as they are generated from the master.

Stand Alone Mode

Select this mode if you are using a custom interface controller. You can select and update all the available parameters.

Generate Byte-Wide Address

Indicates that the internally generated address is byte-wise or for word. The default value is true.

Memory Type

In the memory controller mode, the memory type options are single-port RAM or true dual-port RAM. In stand alone mode, the memory type options are

• Single-port RAM
• Single dual-port RAM
• True dual-port RAM
• Single-port ROM
• Dual-port ROM

Note: In Memory Controller mode, Width and depth parameters calculated and generated by the master (either by AXI BRAM Controller or LMB Controller to which the EMG IP is connected) based on the width selected in the master IP and the Address range set in the Address Editor.

Note: In Memory Controller mode, Embedded Memory Generator does not support Asymmetric port widths or data widths.

Clocking Mode

Select the common clock option when the clock (clka and clkb) inputs are driven by the same clock buffer. Otherwise, select the Independent Clock.

Memory Primitive

In the memory controller mode, the memory primitive options are BRAM and URAM. In stand alone mode, the memory primitives options are:

AUTO

Allow Vivado Synthesis to choose

LUTRAM

Distributed memory

BRAM

Block memory

URAM

UltraRAM memory

MIXED

Mixed RAM Memory.

ECC Mode

The Embedded Memory Generator IP supports following ECC options.

No ECC

Both ECC encoding and decoding are disabled for all utilized write and read ports.

Encode Only

ECC encoding enabled for all utilized write ports.

Decode Only

ECC decoding enabled for all utilized read ports.

Both Encode and Decode

Both ECC encoding and decoding enabled for all utilized write and read ports, respectively.

Memory Depth

Depth of the memory.

Cascade Height

Cascade height of the memory. Its default value is 0 and maximum value is 16 for block RAM and 64 for UltraRAM.

Optimize Unused Memory

Default value is Optimize to enable the optimization of unused memory or bits in the memory structure. Select Do Not Optimize to disable the optimization of unused memory or bits in the memory structure.

Algorithm Options

This parameter provides an option to choose the area optimal implementation. It is possible that all the attributes may lead to same resources.

AUTO

Selects default strategy for synthesis.

Low Power

Selects a strategy to reduce the switching activity of BRAMs and maps using widest configuration possible. Depending on the RTL RAM size, more area might be needed than the default decomposition.

Minimum area

Selects a strategy to reduce the BRAM resource count.

Use Embedded Constraint

Select this option to enable the set_false_path constraint addition between clka of Distributed RAM and doutb_reg on clkb.

Port [A/B] Options

The Port [A/B] options are as follows:

Write Width

Specify the port [A|B] Write width.

Read Width

Select the port [A|B] Read width from the drop-down list of valid choices. The read depth is calculated automatically.

Write Mode Port [A/B]

Specify the port [A|B] write mode.

• READ_FIRST
• WRITE_FIRST
• NO_CHANGE

Read Latency Port [A/B]

Specify the number of register stages in the port [A/B] read data pipeline. Read data output to port douta/doutb takes this number of clka/clkb cycles respectively.

Read Reset Value Port [A/B]

Specify the reset value of the port A/B final output register stage in response to rsta/rstb input port is assertion.

Port [A/B] Byte Wide Write

Selects whether to use the byte-write enable feature

Byte Size(Bits)

Byte size is either 8-bit (no parity) or 9-bit (including parity). The data width of the memory are multiples of the selected byte size.