This register determines the interrupts sources in the Interrupt Status register that are allowed to generate an interrupt. Writing a ‘1’ to a bit enables the corresponding interrupt.
| Bit | Default Value | Access Type | Description |
|---|---|---|---|
| 31 | 0 | R/W | Global Interrupt Enable: Enables the global interrupt. |
| 30:2 | Reserved | ||
| 1 | 0 | R/W | Overflow Interrupt Enable: Enables the overflow interrupt. |
| 0 | 0 | R/W | AES Block Completed Interrupt Enable: Enables the AES block completed interrupt. |