Core Configuration (0x04) - 1.0 English

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)

Document ID
PG308
Release Date
2021-11-10
Version
1.0 English

This register returns the IP Configuration.

Table 1. Receiver Core Configuration (0x04)
Bit Default Value Access Type Description
31:17     RSVD
16   RO I2S Data Width: Indicates the I2S data width of the core.

1 = 24-bit

0 = 16-bit

15:12     RSVD
11:8   RO Number of audio channels: Indicates the number of audio channels supported. Valid values are 2, 4, 6, and 8.
7:1     RSVD
0   RO I2S Master: Indicates if the core has been generated as an I2S master or slave.

1 = I2S Master