This register is used to set the divider value to generate the SCLK. Typically SCLK = 2*24*Fs, where 24 is the I2S data width (this value can also be 16) and Fs is the audio sampling rate.
| Bit | Default Value | Access Type | Description |
|---|---|---|---|
| 31:8 | Reserved | ||
| 7:0 | 0 | R/W | SCLK Out Divider Value: Set a divider value for generation of SCLK. The value of the divider should be such that MCLK/SCLK = Divider_value *2. This register has to be programmed when the core is configured as I2S master. |