IP Facts - 1.0 English

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)

Document ID
PG308
Release Date
2024-05-30
Version
1.0 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 AMD Versal™ adaptive SoC, AMD UltraScale+™ , AMD UltraScale™ , AMD Zynq™ 7000 SoC, 7 series, AMD Zynq™ UltraScale+™ MPSoC.
Supported User Interfaces AXI4-Lite, AXI4-Stream, AXI4
Resources Performance and Resource Use web page for transmitter and Performance and Resource Use web page for receiver.
Provided with Core
Design Files SystemVerilog
Example Design SystemVerilog
Test Bench SystemVerilog
Constraints File Delivered at the time of IP generation
Simulation Model Source HDL
Supported S/W Driver 2 Standalone
Tested Design Flows 3
Design Entry AMD Vivado™ Design Suite, Vivado IP integrator
Simulation For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Records: 70288 (RX), 70699 (TX)
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. Standalone driver details can be found in the AMD Vitis™ software platform directory (<install_directory>/vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver support information is available from the Wiki page.
  3. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).