Audio AXIS Interface - 1.0 English

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)

Document ID
PG308
Release Date
2024-05-30
Version
1.0 English
An AXI4-Stream audio cycle is illustrated in the following figure. The data is valid when both the valid (TVLD) and ready (TRDY) signals are asserted. The I2S Receiver sends out adjacent channels in sequential order (CH0, CH1, etc.). Usually, the I2S Transmitter also expects the channels in sequential order. If the channel data is not in order, then the I2S Transmitter asserts an underflow or block sync error.
Figure 1. Audio AXIS Interface

You must ensure proper pre-emble and TIDs while sending more than two channels of audio data over AXIS. The data width over the AXI4-Stream interface is fixed at 32-bits. All bit positions are as per the IEC60958-3 standard except for the preamble bit format. The preamble provides the start of the audio block and audio channel information. The preamble patterns for the start of block, channelA audio data, and channelB audio data are listed as follows:

Table 1. Audio AXIS Interface Patterns
Bits [3:0] Description
0001 Start of Audio Block/Channel 0 audio sample
0010 Channel 0/2/4/6 audio data - Left Audio Data
0011 Channel 1/3/5/7 audio data - Right Audio Data
Table 2. Audio Input Stream Interface for I2S Transmitter
Ports Direction Width Description
s_axis_aud_aclk Input 1 Clock (the audio streaming clock must be greater than or equal to 128 times the audio sample frequency)
s_axis_aud_aresetn Input 1 Reset (Active-Low)
s_axis_aud__tdata Input 32 Data:
  • [31] P (Parity)
  • [30] C (Channel Status)
  • [29] U (user bit)
  • [28] V (Validity bit)
  • [27:4] Audio Sample word
  • [3:0] Preamble code
  • 4'b0001 Subframe 1/start of audio block
  • 4'b0010 Subframe 1
  • 4'b0010 Subframe 2
s_axis_aud__tid Input 3 Channel ID:

0/2/4/6 audio data - Left Audio Data

1/3/5/7 audio data - Right Audio Data

s_axis_aud__tready Output 1 Ready
s_axis_aud__tvalid Input 1 Valid
Table 3. Audio Output Stream Interface for I2S Receiver
Name Direction Width Description
m_axis_aud_aclk Input 1 Clock (the audio streaming clock must be greater than or equal to 128 times the audio sample frequency)
m_axis_aud_aresetn Input 1 Reset (Active-Low)
m_axis_aud_tdata Output 32 Data:
  • [31] P (Parity)
  • [30] C (Channel Status)
  • [29] U (user bit)
  • [28] V (Validity bit)
  • [27:4] Audio Sample word
  • [3:0] Preamble code
  • 4'b0001 Subframe 1/start of audio block
  • 4'b0010 Subframe 1
  • 4'b0010 Subframe 2
m_axis_aud_tid Output 3 Channel ID
m_axis_aud_tready Input 1 Ready
m_axis_aud_tvaild Output 1 Valid
Note:
  • The Audio sample word is sent on TDATA of AXI4-Stream using bits from 27:4
  • When the I2S Datawidth is 24, all the reserved bits from 27:4 are used to send the data
  • When the I2S Datawidth is 16, the sample data is sent on TDATA[27:12] bits. LSB 8 bits are padded with 0's