The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 11/18/2024 Version 1.0 | |
| Features | Updated the section. |
| Reliability Options Tab | Updated the section to include more information on ECC bypass. |
| Simulation | Updated the section to specify Vivado Simulator support. |
| Memory Controller Register Map | Updated the section to mention register type for ECC, Status, and Activity Monitor Control/Status Registers. |
| 11/02/2022 Version 1.0 | |
| System Level Considerations | Updated Read reorder responses at the AXI interface. |
| 08/06/2021 Version 1.0 | |
| System Level Considerations | Added the use of BRESP necessary to ensure coherency. |
| Lateral AXI Switch Access Throughput | Added data adding conditions in order to prevent switch blocking. |
| General Debugging | If ECC Initialization is used, refresh of Hardware Manager after programming may be required. |
| 01/21/2021 Version 1.0 | |
| Memory Controller Register Map | Added information about new ECC and Status Registers. |
| Data Path Error Protection | Added more information about BRESP error and RRESP error. |
| AXI Port Details | Added more information about read, and write transactions. |
| Lateral AXI Switch Access Throughput Loss | Added information about transactions. |
| 07/31/2020 Version 1.0 | |
| HBM Performance Concepts | Added information about HBM topology, raw throughput evaluation, AXI considerations, HBM address map and protocol considerations, and system-level considerations. |
| Non-Synthesizable Traffic Generator Considerations for Workload Simulation | Added details of Write, Read, Wait, and Start and End Loop commands. |
| PHY Only Mode | Explanation of PHY only mode. |
| General Debugging Checks | Added details of checks to perform for simulation and hardware issues. |
| 10/30/2019 Version 1.0 | |
| Example Design | Added new section Synthesizable Traffic Generator. |
| 08/07/2019 Version 1.0 | |
| General updates | Editorial updates only. No technical content updates. |
| 03/28/2019 Version 1.0 | |
| General updates |
Updated Table 5 and added a table note. Updated Clocking section. |
| 12/05/2018 Version 1.0 | |
| General updates |
Updated figures 3, 4, 5, 6, 7, 8, 9, 10, and 11. Updated AR link. |
| Design Flow Steps |
Added ECC bypass feature. Added pre-defined settings for different traffic. |
| Product Specification |
Added Lateral AXI Switch Access Throughput section. Added Data Path Error Protection section. |
| Debugging | Added Hardware Manager - HBM Debug Interface section. |
| 04/04/2018 Version 1.0 | |
| Initial Xilinx release. | N/A |