The synthesizable traffic generator mode is defined by the value set in the
DEFAULT_MODE parameter for each traffic generator instance at the
top level of the Example Design. By default, this is set to “HBM” but there are
additional modes you can set. The traffic generator only accesses the pseudo channel
address range associated with the AXI port.
- HBM
- This is a high bandwidth Write and read access pattern. Linear aligned addressing sequence where the writes are performed first and then reads back the entire range while checking for data errors with a PRBS pattern. In hardware, this mode covers the entire pseudo channel address range depending on the stack height of the HBM in the device and loops indefinitely. In simulation, this performs 256 32-byte bursts for the Write sequence, 256 32-byte bursts for the read sequence, and then stop.
- HBM_WRITE
- This is a high bandwidth Write only access pattern. A PRBS data pattern is used for the Write only linear aligned addressing sequence. In hardware, this mode covers the entire pseudo channel address range depending on the stack height of the HBM in the device and loops indefinitely. In simulation, this only writes 256 32-byte bursts.
- HBM_READ
- This is a high bandwidth read only access pattern. This is executed as a read only linear aligned addressing sequence. In hardware, this mode covers the entire pseudo channel address range depending on the stack height of the HBM in the device and loops indefinitely. In simulation, this only reads 256 32-byte bursts.
- HBM_W_R
- This is a low bandwidth access pattern because only one write is executed and then the same address is read back. Linear aligned addressing sequence where a single write is followed by a single read. The write and read alternate while linearly progressing through the address space with error checking on a PRBS data pattern. In hardware, this mode covers the entire pseudo channel address range depending on the stack height of the HBM in the device and loops indefinitely. In simulation, this performs a total of 256 32-byte bursts for the write sequence, a total of 256 32-byte bursts for the read sequence, and then stop.
- HBM_RANDOM
- This is an even lower bandwidth access pattern because only one write is executed and then the same address is read back but the traffic generator moves randomly through the address space which means a high probability of a page miss from the previous random address. This mode uses an aligned PRBS addressing sequence where one write is followed by one read with a PRBS data pattern and error checking. In hardware, this mode covers the entire pseudo channel address range depending on the stack height of the HBM in the device and loops indefinitely. In simulation, this performs a total of 256 32-byte bursts for the write sequence, a total of 256 32-byte bursts for the read sequence, and then stop.