AXI High Bandwidth Memory Controller LogiCORE IP Product Guide (PG276) - 1.0 English - PG276

Document ID: PG276
Release Date: 2024-11-18
Version: 1.0 English

Introduction
Features
IP Facts
Overview
Core Overview
Navigating Content by Design Process
Unsupported Features
Licensing and Ordering
Product Specification
Standards
Performance
Lateral AXI Switch Access Throughput Loss
Resource Use
Port Descriptions
AXI Port Details
Non-AXI Ports
Data Path Error Protection
Designing with the Core
Clocking
HBM Performance Concepts
HBM Topology
Raw Throughput Evaluation
AXI Considerations
HBM Address Map and Protocol Considerations
HBM Reordering Options
System-Level Considerations
Non-Synthesizable Traffic Generator Considerations for Workload Simulation
Write and Read Commands
Wait Commands
Start and End Loop Commands
Design Flow Steps
Customizing and Generating the Core
HBM Configuration Selection Tab
Example Design Options Tab
Address Map Options Tab
Reorder, Refresh, and Power Savings Options Tab
Reliability Options Tab
PHY Only Mode
Test Bench
Output Generation
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Implementing the Example Design
Simulating the Example Design
Simulation Results
Non-Synthesizable Traffic Generator
Non-Synthesizable Traffic Generator Commands
WRITE
READ
WAIT
START_LOOP/END_LOOP
SET_DEFAULT
DISPLAY
CSV Examples
Example 1: User-Defined Pattern with Write and Read Command (WRITE, READ)
Example 2: User-Defined Pattern with Loop Command (START_LOOP, END_LOOP)
Example 3: User-Defined Pattern with SET_DEFAULT Command
Example 4: User-Defined Pattern with # (commented out lines)
Example 5: User-Defined Pattern with Amount of Data to be Transferred, Wait by Time, Wait by Clock and Random Bandwidth Distribution
Synthesizable Traffic Generator
Default Behavior of the Synthesizable Traffic Generator
Additional Traffic Modes for the Synthesizable Traffic Generator
Using the VIO Controls
Upgrading
Debugging
Hardware Manager - HBM Debug Interface
Configuration View
General Debugging Checks
Simulation Issues
Hardware Issues
Activity Monitor
Using Activity Monitor
Data Log
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the AXI HBM Controller
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Memory Controller Register Map
Additional Resources and Legal Notices
Support Resources
Finding Additional Documentation
References
Revision History
Please Read: Important Legal Notices

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