- User access to the HBM stacks through AXI3 slave ports
- 16 independent 256-bit ports
- Optional 32-bit data bus extension
- Can be used for either user parity protection or data width
extension
- 64 AXI IDs support per port
- 16 x 16 AXI crossbar switch per HBM stack
- Full memory space access from all AXI ports
- Up to 128 Gb (16 GB) directly addressable data storage in two stack
configuration
- Expansion to 32 AXI ports for dual stack configurations
-
AMBA®
APB 32-bit register bus
access
-
AMD Vivado™
generated initialization
with optional user access port
- Memory performance
- Configurable access reordering to improve bandwidth utilization
- Reordering transactions with different IDs
- Honors ordering rules within IDs
- Read after Write and Write after Write coherency checking for
transactions generated by same master with same ID
- Refresh cycles are handled by the controller
- Temperature controlled refresh rates
- Optional hidden single row refresh option to minimize
overhead
- Increase efficiency based on user access patterns
- Flexible memory address mapping from AXI to the physical HBM
stacks
- Configurable reordering and memory controller behaviors to
optimize latency or bandwidth
- Grouping of Read/Write operations
- Minimizing page opening activation overhead
- Performance monitoring and logging activity registers
- Bandwidth measured at each HBM memory controller
- Configurable sample duration
- Maximum, minimum, and average Read and Write bandwidth is
logged
- Reliability (RAS) support
- Optional SECDED ECC
- Partial word writes supported with Read Modify Write (RMW)
operation
- Background scan of memory for error scrubbing
- Correctable ECC errors found are fixed and updated in memory
- Optional parity with memory access retry due to data parity errors in
Write operations
- Parity data protection available in datapath between user logic
and HBM
- The external parity uses the 32-bit
WDATA_PARITY and RDATA_PARITY buses
with one parity bit per byte of data.
- Uses Odd parity where a 1 is asserted for every data byte when the
sum of the bits in the byte is an odd value.
- Error logging registers
- Power management
- Per memory channel clock gating
- Per memory channel divided clock rate for reduced power
- Power down mode supported
- Optional self-refresh mode to retain contents of memory
- Selectable idle timeout to self-refresh entry
- JEDEC JESD235 HBM2 GEN2 memory stack organization
- 64
Gb density
for
4H
stack or
128
Gb density
for
8H
stack
depending on the device
- 16 independent 64-bit channels
- Optional PHY only interface