|
Core Specifics |
| Supported Device Family
1
|
AMD Virtex™
UltraScale+™
HBM
Devices |
| Supported User Interfaces |
AXI3, AMBA APB |
| Resources |
N/A |
| Provided with Core
|
| Design Files |
Encrypted RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog AXI Traffic Generator |
| Constraints File |
Provided |
| Simulation Model |
Encrypted Verilog |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation (3)
(4)
|
Simulation is supported with Verilog Compliler Simulator (VCS),
Incisive Enterprise Simulator (IES), and Questa Advanced Simulator. For supported
simulator versions, see
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 69267
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
- Behavioral simulations using verilog
simulation models are supported. Netlist (post-synthesis and post-implementation)
simulations are not supported.
- Simulations in 32-bit environments are not
recommended due to the limitation of addressable system memory.
|