The following example describes a simple pattern, 100 writes followed by 100
reads with data integrity checks enabled. The first row specifies a WRITE command to be
repeated 100 times. The AXI transactions are sent to one after the other with zero delay
between them. The first AXI transaction is sent to address 0. The AXI address of
consecutive transactions is incremented by 'h40
.
Therefore, the final transaction is sent to address (100 × 'd64
=' d6400
). After sending the Write
commands, the TG waits for all the Write responses to arrive at the AXI-TG and the
DISPLAY command prints out this information on the console.
Next, a READ command is issued to the AXI-TG. Similar to the WRITE command, 100
Read AXI transactions are issued by the AXI-TG. The AXI address is incremented by
'd64
for each consecutive AXI transaction. Because
the data-integrity checks are enabled, the Read data is compared against the sent Write
data. In the case of any mismatches, the tg_mismatch_error
output signal of AXI_TG is triggered. After all the Read
commands are issued, the TG waits for all the Read data to arrive at the AXI-TG and the
DISPLAY command prints out the information on the console. When all the commands in the
CSV file are completed, axi_tg_done
signal is triggered
by the AXI-TG.