- Select the HBM IP from the Vivado
IP catalog as shown in the following figure.
- Choose the IP settings and click OK.
- Under the Synthesis Options, select the Global option and click Generate.
- Right-click the HBM IP and select, the following window appears Open IP Example Design.
- A new project opens, under the Project Manager, select Settings and click Simulation.
- In the Project Settings under Simulation, select the simulator (VCS
/Questa /IES) that you would want to use as the Target simulator as shown in the following
figure.
- Change the Compiled library location to the location of the compiled library in the installation area.
-
- For VCS simulator: In the Simulation tab, in the vcs.simulate.vcs.more_options enter +notimingcheck
- For Questa simulator: In the Compilation tab questa.compile.vlog.more_options add +notimingchecks
In the Simulation tab questa.simulate.vsim.more_options add +notimingchecks as well.
Also in the Simulation tab questa.simulate.vsim.more_options add -onfinish final. This executes the final block specified by any module when simulation ends.
- For IES simulator, add -notimingchecks in the Elaboration tab ies.elaboration.ncelab.more_options.Note: Only netlist functional simulation supported and users have to pass ‘ -verilog_define NETLIST_SIM’.
- In the Simulation
tab, change the run-time to 1 ms as shown in the following figure.
- Run the simulation.