To integrate the VCU core into an IP integrator (IPI) block design, follow these steps:
- Launch the Vivado IDE and
create a new project.
- Click Next on New Project wizard until you reach the Family Selection window.
- Select a target device for the VCU core.
- Click on the Project Settings window. Click Implementation.
- In the Settings window, enable the Performance Explore option by selecting Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for more information. See the
- Click Create Block Design.
- Click Add IP and type
VCU. The following IP appears.
- Add Zynq UltraScale+ VCU to the block design.
- Add Zynq UltraScale+
MPSoC IP to the block design as shown.
- Configure Zynq UltraScale+ MPSoC to enable AXI slave interfaces, clocking,
and PL-PS interrupt signal per your design requirements. Refer to the
Zynq UltraScale+ MPSoC Processing
System LogiCORE IP Product Guide (PG201) for configuration
options of the Zynq UltraScale+ MPSoC IP.
The following figure shows an example of configuring the PS-PL interface signals.
- Select PL1 clock frequency as 300 MHz.
- Enable IRQ0 [0-7] and enable the following master, slave
interfaces as shown in figure below. Also set the data width of S_AXI_HPC0_FPD to 32 bits.