The following table shows the AXI4 instruction and data cache interface ports of MCU.
| Port | Size (bits) | Direction | Description |
|---|---|---|---|
| vcu_pl_mcu_m_axi_ic_dc_araddr | 44 | Output | AXI4 read address |
| vcu_pl_mcu_m_axi_ic_dc_arburst | 2 | Output | AXI4 read burst type |
| vcu_pl_mcu_m_axi_ic_dc_arcache | 4 | Output | AXI4 ARCACHE value |
| vcu_pl_mcu_m_axi_ic_dc_arid | 3 | Output | AXI4 read master ID |
| vcu_pl_mcu_m_axi_ic_dc_arlen | 8 | Output | AXI4 read burst size |
| vcu_pl_mcu_m_axi_ic_dc_arlock | 1 | Output | AXI4 ARLOCK signal |
| vcu_pl_mcu_m_axi_ic_dc_arprot | 3 | Output | AXI4 ARPROT signal |
| vcu_pl_mcu_m_axi_ic_dc_arqos | 4 | Output | AXI4 ARQOS signal |
| pl_vcu_mcu_m_axi_ic_dc_arready | 1 | Input | AXI4 ARREADY signal |
| vcu_pl_mcu_m_axi_ic_dc_arsize | 3 | Output | AXI4 ARSIZE signal |
| vcu_pl_mcu_m_axi_ic_dc_arvalid | 1 | Output | AXI4 ARVALID signal |
| vcu_pl_mcu_m_axi_ic_dc_awaddr | 44 | Output | AXI4 AWADDR signal |
| vcu_pl_mcu_m_axi_ic_dc_awburst | 2 | Output | AXI4 AWBURST signal |
| vcu_pl_mcu_m_axi_ic_dc_awcache | 4 | Output | AXI4 AWCACHE signal |
| vcu_pl_mcu_m_axi_ic_dc_awid | 3 | Output | AXI4 AWID signal |
| vcu_pl_mcu_m_axi_ic_dc_awlen | 8 | Output | AXI4 AWLEN signal |
| vcu_pl_mcu_m_axi_ic_dc_awlock | 1 | Output | AXI4 AWLOCK signal |
| vcu_pl_mcu_m_axi_ic_dc_awprot | 3 | Output | AXI4 AWPROT signal |
| vcu_pl_mcu_m_axi_ic_dc_awqos | 4 | Output | AXI4 AWQOS signal |
| pl_vcu_mcu_m_axi_ic_dc_awready | 1 | Input | AXI4 AWREADY signal |
| vcu_pl_mcu_m_axi_ic_dc_awsize | 3 | Output | AXI4 AWSIZE signal |
| vcu_pl_mcu_m_axi_ic_dc_awvalid | 1 | Output | AXI4 AWVALID signal |
| pl_vcu_mcu_m_axi_ic_dc_bid | 3 | Input | AXI4 BID signal |
| vcu_pl_mcu_m_axi_ic_dc_bready | 1 | Output | AXI4 BREADY signal |
| pl_vcu_mcu_m_axi_ic_dc_bresp | 2 | Input | AXI4 BRESP signal |
| pl_vcu_mcu_m_axi_ic_dc_bvalid | 1 | Input | AXI4 BVALID signal |
| pl_vcu_mcu_m_axi_ic_dc_rdata | 32 | Input | AXI4 RDATA signal |
| pl_vcu_mcu_m_axi_ic_dc_rid | 3 | Input | AXI4 RID signal |
| pl_vcu_mcu_m_axi_ic_dc_rlast | 1 | Input | AXI4 RLAST signal |
| vcu_pl_mcu_m_axi_ic_dc_rready | 1 | Output | AXI4 RREADY signal |
| pl_vcu_mcu_m_axi_ic_dc_rresp | 2 | Input | AXI4 RRESP signal |
| pl_vcu_mcu_m_axi_ic_dc_rvalid | 1 | Input | AXI4 RVALID signal |
| vcu_pl_mcu_m_axi_ic_dc_wdata | 32 | Output | AXI4 WDATA signal |
| vcu_pl_mcu_m_axi_ic_dc_wlast | 1 | Output | AXI4 WLAST signal |
| pl_vcu_mcu_m_axi_ic_dc_wready | 1 | Input | AXI4 WREADY signal |
| vcu_pl_mcu_m_axi_ic_dc_wstrb | 4 | Output | AXI4 WSTRB signal |
| vcu_pl_mcu_m_axi_ic_dc_wvalid | 1 | Output | AXI4 WVALID signal |
The following table summarizes the AXI4-Lite slave interface ports of the MCU subsystem.
| Port | Width | Direction | Description |
|---|---|---|---|
| pl_vcu_awaddr_axi_lite_apb | 20 | Input | AXI4 AWADDR signal |
| pl_vcu_awprot_axi_lite_apb | 3 | Input | AXI4 AWPROT signal |
| pl_vcu_awvalid_axi_lite_apb | 1 | Input | AXI4 AWVALID signal |
| vcu_pl_awready_axi_lite_apb | 1 | Output | AXI4 AWREADY signal |
| pl_vcu_wdata_axi_lite_apb | 32 | Input | AXI4 WDATA signal |
| pl_vcu_wstrb_axi_lite_apb | 4 | Input | AXI4 WSTRB signal |
| pl_vcu_wvalid_axi_lite_apb | 1 | Input | AXI4 WVALID signal |
| vcu_pl_wready_axi_lite_apb | 1 | Output | AXI4 WREADY signal |
| vcu_pl_bresp_axi_lite_apb | 2 | Output | AXI4 BRESP signal |
| vcu_pl_bvalid_axi_lite_apb | 1 | Output | AXI4 BVALID signal |
| pl_vcu_bready_axi_lite_apb | 1 | Input | AXI4 BREADY signal |
| pl_vcu_araddr_axi_lite_apb | 20 | Input | AXI4 ARADDR signal |
| pl_vcu_arprot_axi_lite_apb | 3 | Input | AXI4 ARPROT signal |
| pl_vcu_arvalid_axi_lite_apb | 1 | Input | AXI4 ARVALID signal |
| vcu_pl_arready_axi_lite_apb | 1 | Output | AXI4 ARREADY signal |
| vcu_pl_rdata_axi_lite_apb | 32 | Output | AXI4 RDATA signal |
| vcu_pl_rresp_axi_lite_apb | 2 | Output | AXI4 RRESP signal |
| vcu_pl_rvalid_axi_lite_apb | 1 | Output | AXI4 RVALID signal |
| pl_vcu_rready_axi_lite_apb | 1 | Input | AXI4 RREADY signal |