Consumer Master AXI Ports - 2024.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)
Document ID
PG252
Release Date
2024-05-30
Version
2024.1 English
Table 1. Consumer Master AXI Write PortX Interface
Signal Direction Description
Write Address Channel
m_axi_mm_x_awid[3:0] Output  
m_axi_mm_x_awaddr [63:0] Output Byte address
m_axi_mm_x_awlen [7:0] Output Length of burst (number of transfer minus 1)
m_axi_mm_x_awsize [2:0] Output Transfer width:
  • 000: 8-bit
  • 001: 16-bit
  • 010: 32-bit
  • 011: 64-bit
m_axi_mm_x_awburst [1:0] Output Burst type:
  • 00: Fixed
  • 01: Incremental
  • 10: Wrapping
  • 11: Reserved
m_axi_mm_x_awvalid Output  
m_axi_mm_x_awready Input  
m_axi_mm_x_awcache[3:0] Output  
m_axi_mm_x_awlock Output  
m_axi_mm_x_awprot[2:0] Output  
m_axi_mm_x_awqos[3:0] Output  
m_axi_mm_x_awuser Output  
Write Data Channel
m_axi_mm_x_wdata [127:0] Output Read data
m_axi_mm_x_wstrb [15:0] Output Byte enable
m_axi_mm_x_wlast Output Not used by the port
m_axi_mm_x_wvalid Input  
m_axi_mm_x_wready Output  
m_axi_mm_x_wuser Output  
Write Response Channel
s_axi_mm_p_x_bid[3:0] Input  
s_axi_mm_p_x_bresp[1:0] Input Tied to zero (OKAY)
s_axi_mm_p_x_bvalid Input  
s_axi_mm_p_x_bready Output  
s_axi_mm_p_x_buser Input  
Table 2. Consumer Master AXI Read PortX Interface
Signal Direction Description
Read Address Channel
m_axi_mm_x_arid[3:0] Output  
m_axi_mm_x_araddr [63:0] Output Byte address
m_axi_mm_x_arlen[7:0] Output Length of burst (number of transfers minus 1)
m_axi_mm_x_arsize[2:0] Output Transfer width:
  • 000: 8-bit
  • 001: 16-bit
  • 010: 32-bit
  • 011: 64-bit
m_axi_mm_x_arburst[1:0] Output Burst type:
  • 00: Fixed
  • 01: Incremental
  • 10: Wrapping
  • 11: Reserved
m_axi_mm_x_arvalid Output  
m_axi_mm_x_arready Input  
m_axi_mm_x_arcache[3:0] Output  
m_axi_mm_x_arlock Output  
m_axi_mm_x_arprot[2:0] Output  
m_axi_mm_x_arqos[3:0] Output  
m_axi_mm_x_aruser Output  
Read Data Channel
m_axi_mm_x_rid[3:0] Input  
m_axi_mm_x_rdata[127:0] Input Read data
m_axi_mm_x_rresp[1:0] Input Tied to zero (OKAY)
m_axi_mm_x_rlast Input  
m_axi_mm_x_rvalid Input  
m_axi_mm_x_rready Output  
m_axi_mm_x_ruser Input