Using QuestaSim - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)
Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

Prior to performing the timing simulation with QuestaSim, the generated design should pass through implementation. All source files in the following directories must be compiled to a single library, as shown in Table: Required QuestaSim Timing Simulation Libraries. See the Synthesis and Simulation Design Guide (UG626) [Ref 13] for instructions on how to compile simulation libraries.

Table 5-2:      Required QuestaSim Timing Simulation Libraries

HDL

Library

Source Directories

Verilog

SIMPRIMS_VER

<Xilinx dir>/verilog/src/simprims
<Xilinx dir>/secureip/mti

VHDL

SIMPRIM

<Xilinx dir>/vhdl/src/simprims/primitive
<Xilinx dir>/secureip/mti

The Wizard provides a command line script for use within QuestaSim. To run a VHDL or Verilog QuestaSim simulation of the wrapper, use these instructions:

1.Launch the QuestaSim simulator and set the current directory to:

<project_directory>/<component_name>/simulation/timing

2.Set the MTI_LIBS variable:

questasim> setenv MTI_LIBS <path to compiled libraries>

3.Launch the simulation script:

questasim> do simulate_mti.do

The QuestaSim script compiles and simulates the routed netlist of the example design and test bench.