The beachfront module must be used along with every instantiation of the GTZE2_OCTAL primitive. This module guarantees the timing of all the synchronous signals across the GTZ transceiver and FPGA logic interface by routing them through pre-locked flip-flops and LUTs. Each input and output signal of the GTZE2_OCTAL passes through this module. Each of the synchronous signals are passed through flip-flops and LUTs that are pre-LOCed.
In addition, the beachfront also has the capability to instantiate the BUFG_LB primitives to generate USERCLKs from OUTCLKs. This functionality is controlled by the parameters listed in Table: TXUSRCLK Attributes on Beachfront. Apart from these parameters, all other parameters seen on the beachfront are the same as the ones that are used on the GTZE2_OCTAL primitive. For more information, see the 7 Series FPGAs GTZ Transceivers User Guide (UG478) [Ref 12].
Table 5-17: TXUSRCLK Attributes on Beachfront
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Parameter
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Description
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TXUSRCLK_SEL_MUX0
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•TXUSRCLK0: Selects the incoming (from FPGA logic) TXUSRCLK0 port to pass on to the GTZE2_OCTAL primitive and also use the same to clock the ports in beachfront. You should take the TXOUTCLK0 output from the beachfront and use an MMCM or a BUFG_LB to generate the user clock.
•TXCORECLK0: Instantiates a BUFG_LB primitive whose input is TXOUTCLK0 and output is TXCORECLK0. The output is passed on to the GTZE2_OCTAL parameter as the TXUSRCLK0, and the same is also used internally to clock beachfront flip-flops. You should use TXCORECLK0 as TXUSRCLK0 in FPGA logic in this case.
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TXUSRCLK_SEL_MUX1
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•TXUSRCLK1: Selects the incoming (from FPGA logic) TXUSRCLK1 port to pass on to the GTZE2_OCTAL primitive and also use the same to clock the ports in beachfront. You should take the TXOUTCLK1 output from the beachfront and use an MMCM or a BUFG_LB to generate the user clock.
•TXCORECLK1: Instantiates a BUFG_LB primitive whose input is TXOUTCLK1 and output is TXCORECLK1. The output is passed on to the GTZE2_OCTAL parameter as the TXUSRCLK1, and the same is also used internally to clock beachfront flip-flops. You should use the TXCORECLK1 as TXUSRCLK1 in the FPGA logic in this case.
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Table: RXUSRCLK Attributes on Beachfront shows the RXUSRCLK attributes on the beachfront module.
Table 5-18: RXUSRCLK Attributes on Beachfront
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Parameter
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Description
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RXUSRCLK_SEL_MUX0
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•RXUSRCLK0: Selects the incoming (from FPGA logic) RXUSRCLK0 port to pass on to the GTZE2_OCTAL primitive and also use the same to clock the ports in beachfront. You should take the RXOUTCLK0 output from the beachfront and use an MMCM or a BUFG_LB to generate the user clock.
•RXCORECLK0: Instantiates a BUFG_LB primitive whose input is RXOUTCLK0 and output is RXCORECLK0. The output is passed on to the GTZE2_OCTAL parameter as the RXUSRCLK0, and the same is also used internally to clock beachfront flip-flops. You should use the RXCORECLK0 as RXUSRCLK0 in FPGA logic in this case.
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RXUSRCLK_SEL_MUX1
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•RXUSRCLK1: Selects the incoming (from FPGA logic) RXUSRCLK1 port to pass on to the GTZE2_OCTAL primitive and also use the same to clock the ports in beachfront. You should take the RXOUTCLK1 output from the beachfront and use an MMCM or a BUFG_LB to generate the user clock.
•RXCORECLK1: Instantiates a BUFG_LB primitive whose input is RXOUTCLK1 and output is RXCORECLK1. The output is passed on to the GTZE2_OCTAL parameter as the RXUSRCLK1, and the same is also used internally to clock beachfront flip-flops. You should use the RXCORECLK1 as RXUSRCLK1 in FPGA logic in this case.
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RXUSRCLK_SEL_MUX2
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•RXUSRCLK2: Selects the incoming (from FPGA logic) RXUSRCLK2 port to pass on to the GTZE2_OCTAL primitive and also use the same to clock the ports in beachfront. You should take the RXOUTCLK2 output from the beachfront and use an MMCM or a BUFG_LB to generate the user clock.
•RXCORECLK2: Instantiates a BUFG_LB primitive whose input is RXOUTCLK1 and output is RXCORECLK2. The output is passed on to the GTZE2_OCTAL parameter as the RXUSRCLK2, and the same is also used internally to clock beachfront flip-flops. You should use the RXCORECLK2 as RXUSRCLK2 in FPGA logic in this case.
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RXUSRCLK_SEL_MUX3
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•RXUSRCLK3: Selects the incoming (from FPGA logic) RXUSRCLK3 port to pass on to the GTZE2_OCTAL primitive and also use the same to clock the ports in beachfront. You should take the RXOUTCLK3 output from the beachfront and use an MMCM or a BUFG_LB to generate the user clock.
•RXCORECLK3: Instantiates a BUFG_LB primitive whose input is RXOUTCLK3 and output is RXCORECLK3. The output is passed on to the GTZE2_OCTAL parameter as the RXUSRCLK3, and the same is also used internally to clock beachfront flip-flops. You are supposed to use the RXCORECLK3 as RXUSRCLK3 in FPGA logic in this case.
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Input ports to the beachfront from the FPGA logic are prefixed with B2M_. Output ports from the beachfront going to the FPGA logic are prefixed with M2B_. Thus, you should always use either the M2B_ or B2M_ ports of the beachfront to connect to the GTZE2_OCTAL. Apart from the ports listed in Table: TX/RXCORECLK Ports on Beachfront, all other ports on the beachfront interface are the same as the ones seen in the GTZE2_OCTAL primitive. For more information, see the 7 Series FPGAs GTZ Transceivers User Guide (UG478) [Ref 12].
Table 5-19: TX/RXCORECLK Ports on Beachfront
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Port
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Direction
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Description
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TXCORECLK0
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Output
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This port should be used as TXUSRCLK0 if the parameter TXUSRCLK_SEL_MUX0 is set to TXCORECLK0; else this port should be ignored.
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TXCORECLK1
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Output
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This port should be used as TXUSRCLK1 if the parameter TXUSRCLK_SEL_MUX1 is set to TXCORECLK1; else this port should be ignored.
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TXCORECLK0
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Output
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This port should be used as TXUSRCLK1 if the parameter TXUSRCLK_SEL_MUX1 is set to TXCORECLK1; else this port should be ignored.
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RXCORECLK0
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Output
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This port should be used as RXUSRCLK0 if the parameter RXUSRCLK_SEL_MUX0 is set to RXCORECLK0; else this port should be ignored.
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RXCORECLK1
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Output
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This port should be used as RXUSRCLK1 if the parameter RXUSRCLK_SEL_MUX1 is set to RXCORECLK1; else this port should be ignored.
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RXCORECLK2
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Output
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This port should be used as RXUSRCLK2 if the parameter RXUSRCLK_SEL_MUX2 is set to RXCORECLK2; else this port should be ignored.
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RXCORECLK3
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Output
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This port should be used as RXUSRCLK3 if the parameter RXUSRCLK_SEL_MUX3 is set to RXCORECLK3; else this port should be ignored.
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