7 Series FPGA Transceiver Core Reference Clock Constraint - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

The number of reference clocks is derived based on transceiver selection. The Reference Clock (MHz) value selected in the second tab of the Vivado IDE is used to constrain the required reference clock. The create_clock XDC command is used to constrain all necessary required reference clocks.