RECOMMENDED: For debugging, Xilinx strongly recommends setting the synthesis option for -flatten_hierarchy to none or rebuilt. Enable the filtering according to hierarchy to preserve netlist hierarchy and easing the process of signal location.
Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into your design. The debug feature allows you to set trigger conditions to capture application and integrated block port signals in hardware. Captured signals can then be analyzed. This feature represents the functionality in the Vivado IDE that is used for logic debugging and validation of a design running in Xilinx devices in hardware.
The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:
•ILA 3.0 (and later versions)
•VIO 3.0 (and later versions)
See the Vivado Design Suite User Guide: Programming and Debugging [Ref 15].