Other Changes - 3.6 English - PG168

7 Series FPGAs Transceivers Wizard (PG168)

Document ID: PG168
Release Date: 2022-05-19
Version: 3.6 English

7 Series FPGAs Transceivers Wizard v3.6 LogiCORE IP Product Guide
IP Facts
Introduction
Features
Overview
About the Wizard
Functional Overview
Structure of the Transceiver Wrapper, Example Design, and Test Bench
Feature Summary
Applications
Unsupported Features
Licensing and Ordering
Product Specification
Performance
Maximum Frequencies
Port Descriptions
Designing with the Core
General Design Guidelines
Serial Transceiver Location
Use the Example Design as a Starting Point
Keep It Registered
Recognize Timing Critical Signals
Use Supported Design Flows
Make Only Allowed Modifications
Clocking
Generation of TX/RXUSRCLK and TX/RXUSRCLK2
Instantiation of MMCM/BUFG
Resets
Reset Finite State Machine
Reset Sequence Modules for GTH and GTP Transceivers
Design Flow Steps
Customizing and Generating the Core
Component Name
Example Design—XAUI Configuration
Setting the Project Options
Configuring and Generating the Wrapper
GTZ Transceivers
Octal Selection, Channel Selection, Line Rate, and REFCLK
Clocking
PCS Modes
Optional Ports
Summary
GTX, GTH, and GTP Transceivers
GT Type Selection
Line Rate, Transceiver Selection, and Clocking
Encoding and Optional Ports
Alignment, Termination, and Equalization
PCI Express, SATA, OOB, PRBS, Channel Bonding, and Clock Correction Selection
Channel Bonding and Clock Correction Sequence
Summary
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
7 Series FPGA Transceiver Core Reference Clock Constraint
False Paths
Example Design
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Functional Simulation Using the Vivado Design Tools
Using QuestaSim
Implementing Using the Vivado Design Tools
Timing Simulation Using the Vivado Design Tools
Using QuestaSim
Using Vivado Design Suite Debug Feature with the Wizard
Directory and File Contents
<project directory>
<component name>/<component name>.data
<component name>/<component name>.srcs
<component name>/<component name>_example design
Output Generation
Directory and File Contents
<project directory>\example_project
<component name>_example.src\sources_1
constrs_1\imports\example_design
sim_1\imports\simulation
source_1\ip\<component name>
<component name>\
ip\<component name>\example_design\
imports\<component name>
<example_design>\<support>
<component name>_example.srcs/sim_1/imports/simulation
Example Design Description for GTX, GTH, and GTP Transceivers
Reset Finite State Machine
CTLE3 Adaptation Modules for GTX Transceivers
CTLE AGC Comp – CTLE3 Adaptation
Example Design Hierarchy
Reset Sequence Modules for GTH and GTP Transceivers
Example Design Description for GTZ Transceivers
Reset and CTLE Tuning
Beachfront Module
Dynamic Phase Deskew
Multi-Lane Mode
Using The Example Design in Hardware
Example Design Hierarchy
Known Limitations of the GTZ Wizard
Known Limitations of the Wizard
Verification, Compliance, and Interoperability
Simulation
Hardware Testing
Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Prerequisites
Overview of Major Changes
Block Diagram
Shared Logic Use Models with Multiple Instances
Constraints
Signal Changes
Migration Steps
Vivado Design Suite Debug Feature Option
Transceiver Core Debug
Change Log Information
Parameter Changes
Port Changes
Other Changes
Debugging
Finding Help on Xilinx.com
Documentation
Solution Centers
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Wizard Validation
Wizard Validation Scope
Datapath Testing
Different PLL Testing
Loopback Mode Testing
PRBS Mode Testing
TX/RX Buffer Testing
REFCLK Testing
Powerdown Testing
TX/RX Rate-change Testing
TX/RX Polarity Testing
TX/RX Electrical Idle Testing
Encoding and Decoding Testing
Comma Detection Testing
Comma Alignment Testing
TX/RX OOB Testing
TX/RX PCIe Beacon Testing
PCIe Receiver Detection Testing
Channel-bond Testing
Clock-correction Testing
TX/RX USERCLK Testing
Reset Testing
Simulation Debug
Next Step
Hardware Debug
Loopback Limitations
GT Debug Using IBERT
Debugging Using Serial I/O Analyzer
Debugging Using Embedded BERT
7\ Series GT Wizard Hardware Validation on the KC705 Evaluation Board
Setup Requirements
Software
Hardware
GTX Transceiver Validation
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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