The 7 series FPGAs Transceivers Wizard core example design has specific prerequisites that the simulation environment and the test bench must fulfill. These are described in the following sections. See the latest version of the Synthesis and Simulation Design Guide (UG626) [Ref 13] for more information on simulator dependency on hardware description language (HDL).
The prerequisites for the simulation environment are:
•A simulator with support for SecureIP models.
•A mixed-language simulator for VHDL simulation.
•An installed GTX/GTH/GTP transceiver SecureIP model.
•The ability to run COMPXLIB, which compiles the simulation libraries (for example, UNISIM, SIMPRIMS) in the correct order.
•The correct setup of the simulator for SecureIP use (initialization file, environment variables).
•The correct simulator resolution (Verilog).
If the channel does do not come up in simulation:
•Ensure that DRP_CLK and SYSCLK are driven correctly.
•The quickest way to debug these problems is to view the signals from one of the serial transceiver instances that are not working.
•Make sure that the serial transceiver reference clock and user clocks are all toggling.
Note: Only one of the reference clocks should be toggling. The rest will be tied Low.
•Check to see that RECCLK and TXOUTCLK from the serial transceiver wrapper are toggling. If not toggling, you might have to wait longer for the PMA to finish locking. You should typically wait about 6 to 9 microseconds for the channel to come up. You might need to wait longer for simplex designs and 7\ series FPGA designs.
•Make sure that TXN and TXP are toggling. If they are not, make sure you have waited long enough (see the previous bullet) and make sure you are not driving the TX signal with another signal.
•Check the GTTXRESET, GTRXRESET, CPLLRESET, QPLLRESET, PLL0RESET, and PLL1RESET signals in your design. If these are being held active, your 7 series transceiver module will not be able to initialize.
•Check if the CPLLLOCK, QPLLLOCK, TXRESETDONE, and RXRESETDONE signals are asserted. If they are not, look into the state machines in the Init module.
•Be sure you do not have the POWER_DOWN, TXPD, and RXPD signals asserted.
•Make sure the TXN and TXP signals from each transceiver are connected to the appropriate RXN and RXP signals from the corresponding transceiver on the other side of the channel.
•If you are using a multi-lane channel, make sure all the serial transceivers on each side of the channel are connected in the correct order.
•If you are simulating Verilog, you need to instantiate the glbl module and use it to drive the power_up reset at the beginning of the simulation to simulate the reset that occurs after configuration. You should hold this reset for a few cycles.
The following code can be used an example:
// simulate the global reset that occurs after configuration
// at the beginning of the simulation
assign glbl.GSR = gsr_r;
assign glbl.GTS = gts_r;
initial
begin
gts_r = 1'b0;
gsr_r = 1'b1;
#(16*CLOCKPERIOD_1);
gsr_r = 1'b0;
end
If the channel comes up in simulation but not in hardware:
•Make sure the REFCLK frequency is exactly the same as the input in the 7\ series FPGA transceiver core-generated Wizard.
•Make sure that the DRP clock is constrained properly in the XDC. See the 7\ series data sheets for more information.
•When the DRP interface is enabled, DRP_CLK is connected to SYSCLK in the example design. Thus, make sure that SYSCLK is also constrained properly in the XDC when it is enabled.
•If REFCLK is driven from a synthesizer, make sure the synthesizer (PLL/MMCM_NOT_LOCKED) is stable (locked).
•Make sure the cable connection from TXP/TXN to RXP/RXN is proper.
•Make sure that the transceiver locations are properly set in XDC as chosen from the Wizard.
•If there are RXNOTINTABLE errors observed from the serial transceiver, validate the link using IBERT. Make sure there is no BER in the channel. Use the sweep test in the IBERT tool and use the same serial transceiver attributes that provide zero BER in IBERT.
•Make sure all the signals at the transceiver interface are toggling correctly. All necessary signals needed to debug should be captured in the Vivado Design Suite debug feature if you are debugging in hardware.
Problems while compiling the design:
•Make sure you include all the files from the src directory when compiling.