The example design that is delivered with the wrappers helps designers understand how to use the wrappers and transceivers in a design.
The example design connects a frame generator and a frame checker to the wrapper. The frame generator transmits an incrementing counting pattern while the frame checker monitors the received data for correctness. The frame generator counting pattern is stored in the block RAM. This pattern can be easily modified by altering the parameters in the gt_rom_init_tx.dat and gt_rom_init_rx.dat files. The frame checker contains the same pattern in the block RAM and compares it with the received data. An error counter in the frame checker keeps track of how many errors have occurred.
The example design also demonstrates how to generate the USRCLKs out of the OUTCLKs coming out of an octal. Also note the connections of USRCLKs for octal0 and octal1. Properly configured clock module wrappers are also provided if they are required to generate user clocks for the instantiated transceivers. The logic for scrambler, descrambler, and block synchronization is instantiated in the example design for 64B/66B. The frame_gen_top module also shows how to drive the txsequence counter and how to pause the data and header controls based on the sequence counter values. The USRCLK source module shows how and when an MMCM is required to generate a USRCLK.
The example design can be synthesized using XST or the Vivado tools and implemented with the Vivado tools. It can be simulated using VCS or Cadence Incisive Unified Simulator (IUS).