Vivado Design Suite Debug Feature - 8.2 English

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8.2 English

The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly

into your design. The debug feature also allows you to set trigger conditions to capture

application and integrated block port signals in hardware. Captured signals can then be

analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a

design running in Xilinx devices.

The Vivado logic analyzer is used with the logic debug IP cores, including:

ILA 2.0 (and later versions)

VIO 2.0 (and later versions)

See Vivado Design Suite User Guide: Programming and Debugging ( UG908 ) [Ref 5] .