|
Signal Name
|
Direction
|
Width
|
Description
|
|
s_axi_CTRL_awvalid
|
In
|
1
|
AXI4-Lite Write Address Channel Write Address Valid.
|
|
s_axi_CTRL_awready
|
Out
|
1
|
AXI4-Lite Write Address Channel Write Address Ready. Indicates DMA ready to accept the write address.
|
|
s_axi_CTRL_awaddr
|
In
|
8
|
AXI4-Lite Write Address Bus
|
|
s_axi_CTRL_wvalid
|
In
|
1
|
AXI4-Lite Write Data Channel Write Data Valid.
|
|
s_axi_CTRL_wready
|
Out
|
1
|
AXI4-Lite Write Data Channel Write Data Ready. Indicates DMA is ready to accept the write data.
|
|
s_axi_CTRL_wdata
|
In
|
32
|
AXI4-Lite Write Data Bus
|
|
s_axi_CTRL_bresp
|
Out
|
2
|
AXI4-Lite Write Response Channel. Indicates results of the write transfer.
|
|
s_axi_CTRL_bvalid
|
Out
|
1
|
AXI4-Lite Write Response Channel Response Valid. Indicates response is valid.
|
|
s_axi_CTRL_bready
|
In
|
1
|
AXI4-Lite Write Response Channel Ready. Indicates target is ready to receive response.
|
|
s_axi_CTRL_arvalid
|
In
|
1
|
AXI4-Lite Read Address Channel Read Address Valid
|
|
s_axi_CTRL_arready
|
Out
|
1
|
Ready. Indicates DMA is ready to accept the read address.
|
|
s_axi_CTRL_araddr
|
In
|
8
|
AXI4-Lite Read Address Bus
|
|
s_axi_CTRL_rvalid
|
Out
|
1
|
AXI4-Lite Read Data Channel Read Data Valid
|
|
s_axi_CTRL_rready
|
In
|
1
|
AXI4-Lite Read Data Channel Read Data Ready. Indicates target is ready to accept the read data.
|
|
s_axi_CTRL_rdata
|
Out
|
32
|
AXI4-Lite Read Data Bus
|
|
s_axi_CTRL_rresp
|
Out
|
2
|
AXI4-Lite Read Response Channel Response. Indicates results of the read transfer.
|
|
s_axi_CTRL_wstrb
|
In
|
4
|
AXI4-Lite Write Strobe. Shows which bytes of the data bus are valid and should be read by the Slave.
|