• Color bars
• Zone plate with adjustable sweep and speed
• Temporal and spatial ramps
• Moving box with selectable size and color over any available test pattern
• RGB, YUV 444, YUV 422, YUV 420
• AXI4-Stream data interfaces
• AXI4-Lite control interface
• Supports 8, 10, 12, and 16-bits per component input and output
• Supports spatial resolutions from 64 x 64 up to 15360 x 8640
° Supports 8K60 in all supported device families ( 1 )
1. Performance on low power devices may be lower.
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LogiCORE IP Facts Table |
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|---|---|---|---|---|---|
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Core Specifics |
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Versal® ACAP, UltraScale+™ Families, UltraScale™ Architecture, 7 Series |
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Supported User Interfaces |
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Resources |
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Provided with Core |
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Documentation |
Product Guide |
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Design Files |
Not Provided |
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Example Design |
Yes |
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Test Bench |
Not Provided |
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Constraints File |
XDC |
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Simulation Models |
Encrypted RTL, VHDL, or Verilog Structural |
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Standalone, V4L2 |
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Design Entry Tools |
Vivado ® Design Suite |
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Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
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Synthesis Tools |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 54536 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete listing of supported devices, see the Vivado IP Catalog. 2. Video protocol as defined in the Video IP: AXI Feature Adoption section of AXI Reference Guide [Ref 1] . 3. Standalone driver details can be found in the Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm). 4. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide . |
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