Features - 8.2 English

Video Test Pattern Generator

Document ID
Release Date
8.2 English

Color bars

Zone plate with adjustable sweep and speed

Temporal and spatial ramps

Moving box with selectable size and color over any available test pattern

RGB, YUV 444, YUV 422, YUV 420

AXI4-Stream data interfaces

AXI4-Lite control interface

Supports 8, 10, 12, and 16-bits per component input and output

Supports spatial resolutions from 64 x 64 up to 15360 x 8640

° Supports 8K60 in all supported device families ( 1 )

1. Performance on low power devices may be lower.

LogiCORE IP Facts Table

Core Specifics

Supported Device Family ( 1 )

Versal® ACAP, UltraScale+™ Families,

UltraScale™ Architecture, 7 Series

Supported User Interfaces

AXI4-Lite, AXI4-Stream ( 2 )


Performance and Resource Utilization web page

Provided with Core


Product Guide

Design Files

Not Provided

Example Design


Test Bench

Not Provided

Constraints File


Simulation Models

Encrypted RTL, VHDL, or Verilog Structural

Supported Software Drivers ( 3 )

Standalone, V4L2

Tested Design Flows ( 4 )

Design Entry Tools

Vivado ® Design Suite


For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Synthesis Tools

Vivado Synthesis


Release Notes and Known Issues

Master Answer Record: 54536

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page.


1. For a complete listing of supported devices, see the Vivado IP Catalog.

2. Video protocol as defined in the Video IP: AXI Feature Adoption section of AXI Reference Guide [Ref 1] .

3. Standalone driver details can be found in the Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm).

4. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide .