The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
11/04/2022 |
8.2 |
General updates. |
|
05/11/2022 |
8.2 |
•Updated Register Names and Register Description in Table: Register Names and Descriptions . •Updated Control (0x0000) Register . •Updated Table: Example Design Support . |
|
11/10/2021 |
8.2 |
Added support for 15360 x 8640 resolution. |
|
08/06/2021 |
8.1 |
Provided Versal Example design along with the IP. |
|
02/04/2021 |
8.1 |
General updates. |
|
12/17/2019 |
8.0 |
Updated the Synthesizable Design Section with new Vitis flow for software. |
|
12/05/2018 |
8.0 |
Added interlaced video support. Added 10k video resolution support. Removed license from the core. |
|
04/05/2017 |
7.0 |
Updated Customizing and Generating the Core section. |
|
10/05/2016 |
7.0 |
Added DisplayPort patterns. Added 8 pixel-per-clock and 8K resolution supports. Provided pattern configurability and flexibility. Updated Xilinx automotive applications disclaimer. |
|
11/18/2015 |
7.0 |
Added UltraScale+ support. |
|
09/30/2015 |
7.0 |
Redesigned IP with Vivado HLS. Documented interface changes. Added example design. |
|
10/01/2014 |
6.0 |
Removed Application Software Development appendix. |
|
04/02/2014 |
6.0 |
Added Video Timing Input interface. |
|
10/02/2013 |
5.0 |
Synch document version with core version. Updated Constraints and Test Bench chapters. Updated Migration appendix. |
|
03/20/2013 |
1.1 |
Updated for core version. Removed ISE chapters. |
|
12/18/2012 |
1.0 |
Initial Xilinx release of Product Guide. |