The following table shows the revision history for this document.
Section | Revision Summary |
---|---|
7/24/2024 Version 1.5 | |
Absolute Maximum Ratings | Added VCCINT_GT specification. |
Power Supply Requirements | Added reference links. |
AC Switching Characteristics | Updated to the Vivado Design Suite version to 2024.1.1. |
Table 5 | Updated the overdrive voltage in Note 7. |
DDR4 and LPDDR4/4X Memory Interface Controller | Updated Note 5. |
Table 2 | Revised VIDIFF maximum. |
GTM Transceiver User Clock Switching Characteristics | Changed the -1M and -1L frequencies for PAM4 FTXIN and FRXIN. |
Table 2 | Revised VIDIFF maximum. |
GTYP Transceiver Reference Clock Oscillator Selection Phase Noise Mask | Interchanged symbols LCPLL and RINGPLL. |
Programmable Logic Integrated Block for PCIe | Added a note to each table in this section to clarify that the specifications are only for the integrated blocks for PCIe. |
Integrated Blocks for PCIe with DMA and Cache Coherent Interconnect (CPM) | Added a note to each table in this section to clarify that the specifications are only for the integrated blocks for PCIe. |
2/29/2024 Version 1.4 | |
General updates |
Updated Table 1 including production release using the Vivado Design Suite 2023.2.1 v2.02: XCVH1742 and XCVH1782 devices with speed grades -3HSE, -2LSE, -2LLE, and -1LSE. This includes updates to the following tables: |
Absolute Maximum Ratings | Revised the transceiver REFCLK_AC maximum input voltage from 1.200V to 1.350V. |
Block RAM Switching Characteristics | Changed maximum value of TRCKO_DO_REG in the -2L speed grade from 0.333 ns to 0.344 ns. |
DDR4 and LPDDR4/4X Memory Interface Controller | Removed the LPDDR4/4X pin efficient component interface limitation (Note 6). |
Table 2 | Added the VICM specification. To support LVPECL clocks, changed the VIDIFF maximum (peak-to-peak) to 800 mV. |
GTM Transceiver Performance | Added Note 1. |
GTM Transceiver PLL/Lock Time Adaptation | Update the TDLOCK values for GTM PAM4. |
Table 2 | Added the VICM specification. To support LVPECL clocks, changed the VIDIFF maximum (peak-to-peak) to 800 mV. |
10/31/2023 Version 1.3 | |
General updates | Updated the Table 1 including production release using
the Vivado Design Suite 2023.2 v2.01:
|
Table 2 | Revised both the TSTG and Tj maximum temperatures to 120°C. |
Recommended Operating Conditions | Updated Tj specifications and Note 15. |
Updated Note 8 with information on the PSIO. | |
Updated Note 9. | |
Available Speed Grades and Operating Voltages | Updated Note 3. |
DC Characteristics Over Recommended Operating Conditions | Updated Note 3 to clarify how to design with specific devices. |
DDR4 and LPDDR4/4X Memory Interface Controller | Updated the LPDDR4/LPDDR4X rows and added Note 6. |
Network on Chip Switching Characteristics | Added FMAX_NMU_HBM to the table. |
GTM Transceiver Reference Clock Switching Characteristics | Added Note 1. |
GTM Transceiver Digital Monitor Clock | Added table. |
GTYP Transceiver Reference Clock Switching Characteristics | Added Note 1. |
GTYP Transceiver Digital Monitor Clock | Added table. |
9/08/2023 Version 1.2 | |
General updates | Updated the Table 1 including production release of the XCVH1522, XCVH1542, and XCVH1582 devices with
speed grades -3HSE, -2MSE, -2MLE, -1MSE using the Vivado Design Suite 2023.1.2 v2.00. This includes updates to Speed Grade Designations, Production Silicon and Software Status, Device Pin-to-Pin Output Parameter Guidelines, and Device Pin-to-Pin Input Parameter Guidelines. |
Device Identification | Updated each IDCODE[31:0]. |
GTYP Transceiver Electrical Compliance | Clarified PCIe support. |
6/08/2023 Version 1.1 | |
Absolute Maximum Ratings | Revised the IDCIN_GTM_AVTT and IDCIN_GTM_GND values from 12 mA to 16 mA. Added Note 10. |
Recommended Operating Conditions | Updated VCC_PMC to include overdrive voltages and updated Note 15. |
Available Speed Grades and Operating Voltages | Updated Note 1 to specifically state that unless noted otherwise, the overdrive performance values are the same as standard mode. |
DC Characteristics Over Recommended Operating Conditions | Added IL value and added Note 3 to the CIN and IRPU values to be used for devices with super-logic regions (SLRs). |
Table 4 | Added Notes 1, 2, and 3. |
Table 5 | Added Notes 2, 3, 4, 5, 6, and 7. |
PS Gigabit Ethernet MAC Controller Interface | Added Note 2 to the gigabit Ethernet MAC time-stamp unit reference clock frequency (FGEMTSUREFCLK). |
Clock Buffers and Networks | Updated the values in Table 1 to include FMAX specifications by device. |
GTM Transceiver DC Input and Output Levels | Added specifications for VCMOUTDC . |
GTYP Transceiver DC Input and Output Levels | Removed the row for VCMOUTDC when remote RX is terminated to GND and added Note 2. Updated Note 3. |
GTYP Transceiver Electrical Compliance | Updated to add the PCIe Gen 4 and Gen 5 protocols. |
High Bandwidth Memory Controller | Revised the LVCMOS external reference clock maximum frequency to 125 MHz. |
1/27/2023 Version 1.0 | |
Initial release. | N/A |