The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.
Symbol | Description | Device | Performance as a Function of Speed Grade and Operating Voltage (VCCINT) | Units | |||||
---|---|---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||||
-3 | -2 | -1 | -2 | -1 | |||||
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3 | |||||||||
TSUMMCM_VH1522 | Global clock input and input flip-flop (or latch) with MMCM | Setup | XCVH1522 | –1.01 | –1.02 | –1.02 | –1.02 | –1.07 | ns |
THMMCM_VH1522 | Hold | 4.27 | 4.71 | 4.93 | 4.71 | 4.94 | ns | ||
TSUMMCM_VH1542 | Setup | XCVH1542 | –1.01 | –1.02 | –1.02 | –1.02 | –1.07 | ns | |
THMMCM_VH1542 | Hold | 4.27 | 4.71 | 4.93 | 4.71 | 4.94 | ns | ||
TSUMMCM_VH1582 | Setup | XCVH1582 | –1.01 | –1.02 | –1.02 | –1.02 | –1.07 | ns | |
THMMCM_VH1582 | Hold | 4.27 | 4.71 | 4.93 | 4.71 | 4.94 | ns | ||
TSUMMCM_VH1742 | Setup | XCVH1742 | –1.01 | –1.02 | –1.02 | –1.02 | –1.07 | ns | |
THMMCM_VH1742 | Hold | 4.27 | 4.71 | 4.93 | 4.71 | 4.94 | ns | ||
TSUMMCM_VH1782 | Setup | XCVH1782 | –1.01 | –1.02 | –1.02 | –1.02 | –1.07 | ns | |
THMMCM_VH1782 | Hold | 4.27 | 4.71 | 4.93 | 4.71 | 4.94 | ns | ||
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