Programmable Logic Performance Characteristics

Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960)

Document ID
DS960
Release Date
2024-07-24
Revision
1.5 English

This section provides the performance characteristics of some common functions and designs implemented in the Versal HBM devices. These values are subject to the same guidelines as the AC Switching Characteristics section.

In each of the following performance tables, the I/O bank type is XPIO.

Table 1. I/O Logic Performance
Description Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
Min Max Min Max Min Max Min Max Min Max
TX DDR 0 250 0 250 0 250 0 200 0 200 Mb/s
TX SDR 0 125 0 125 0 125 0 100 0 100 Mb/s
RX DDR 0 250 0 250 0 250 0 200 0 200 Mb/s
RX SDR 0 125 0 125 0 125 0 100 0 100 Mb/s
Table 2. XPHY I/O Performance
Description 1, 2 Data Width Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
Min Max Min Max Min Max Min Max Min Max
TX DDR 8 200 1800 200 1800 200 1800 200 1800 200 1800 Mb/s
4 200 1600 200 1468 200 1468 200 1332 3 200 1332 3 Mb/s
2 200 800 200 734 200 734 200 666 4 200 666 4 Mb/s
RX DDR 5 8 200 1800 200 1800 200 1800 200 1800 200 1800 Mb/s
4 200 1600 200 1468 200 1468 200 1332 3 200 1332 3 Mb/s
2 200 800 200 734 200 734 200 666 4 200 666 4 Mb/s
  1. XPHY I/O is supported through the Advanced I/O Wizard available with the Vivado Design Suite. The performance values assume a source-synchronous interface. For asynchronous interfaces, see the Advanced I/O Wizard LogiCORE IP Product Guide (PG320).
  2. Package skews are not included and should be removed through PCB routing.
  3. For multi-bank interfaces, the performance is specified at 1066.5 Mb/s.
  4. For multi-bank interfaces, the performance is specified at 533.25 Mb/s.
  5. SDR specifications are a subset of the DDR specifications.
Table 3. MIPI D-PHY Performance
Description I/O Bank Type Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
MIPI D-PHY transmitter or receiver XP 3200 3200 3200 3200 3200 Mb/s
Table 4. Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller
Memory Standard DRAM Type DIMM Slots XPIO Bank Performance 1 Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
DDR4 Single rank component All 3200 2933 2667 2667 2133 Mb/s
1 rank RDIMM, DIMM 2 1 All 3200 2933 2667 2133 2133 Mb/s
2 rank RDIMM, LRDIMM, DIMM 2 1 All 2933 2667 2667 2133 2133 Mb/s
4 rank LRDIMM 1 All 2667 2400 2400 2133 2133 Mb/s
1 rank RDIMM 2 All 2667 2400 2400 2133 2133 Mb/s
1 rank DIMM 2 2 All 2400 2133 2133 1867 1867 Mb/s
2 rank LRDIMM 2 All 2667 2400 2400 2133 2133 Mb/s
2 rank RDIMM 2 All 2133 2133 2133 2133 2133 Mb/s
2 rank DIMM 2 2 All 1866 1866 1866 1866 1866 Mb/s
RLDRAM3 All 1066 1066 1066 1066 4 1066 4 MHz
QDRIV HP All 933 933 933 933 933 MHz
XP 3 All 1066 1066 1066 1066 1066 MHz
  1. The Versal device package pinout files specify XPIO bank performance (XPIOperf). See ASCII package files information in the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).
  2. Dual in-line memory module (DIMM) includes SODIMM and UDIMM.
  3. The QDRIV XP performance values are for 18-bit interfaces, for 36-bit interfaces the maximum performance is 933 MHz.
  4. The RLDRAM3 maximum performance with burst length 2 (BL2) interfaces is 933 MHz in the -2L and -1L speed grades.