Symbol | Description | Min | Max | Units |
---|---|---|---|---|
FREFCLK | Reference clock (REF_CLK) frequency | 27 | 60 | MHz |
TRMSJ_REFCLK | REF_CLK input RMS clock jitter | – | 3 | ps |
TINPJ_REFCLK |
REF_CLK input period jitter (peak-to-peak) Number of clock cycles = 10,000 |
– | 50 | ps |
TDC_REFCLK | REF_CLK duty cycle | 45 | 55 | % |
TREFCLK | REF_CLK rise time (20%–80%) and fall time (80%–20%) at 3.3V | – | 3 | ns |
REF_CLK rise time (20%–80%) and fall time (80%–20%) at 1.8V or 2.5V | – | 3.5 | ns | |
REF_CLK rise time (10%–90%) and fall time (90%–10%) at 3.3V | – | 4 | ns | |
REF_CLK rise time (10%–90%) and fall time (90%–10%) at 1.8V or 2.5V | – | 4.66 | ns | |
|
Symbol | Description | Min | Typ | Max | Units |
---|---|---|---|---|---|
FXTAL | Parallel resonance crystal frequency | – | 32.768 | – | kHz |
TFTXTAL | Frequency tolerance | –20 | – | 20 | ppm |
CXTAL | Load capacitance for crystal parallel resonance | – | 12.5 | – | pF |
RESR | Crystal ESR (16.8 and 19.2 MHz) | – | 70 | – | kΩ |
CSHUNT | Crystal shunt capacitance | – | 1.4 | – | pF |
Symbol | Description | Min | Typ | Max | Units |
---|---|---|---|---|---|
TPOR_B | Required POR_B assertion time 1, 2 | 10 | – | – | µs |
TMODEPOR | MODE[3:0] setup time to POR_B rising edge | 74 | – | – | ns |
TPORMODE | POR_B rising edge to MODE[3:0] hold time | 74 | – | – | ns |
|
Symbol | Description | Performance as a Function of Speed Grade and Operating Voltage (VCC_PSFP) | Units | ||||
---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||
-3 | -2 | -1 | -2 | -1 | |||
FFPD_LSBUS_CLK | Maximum FPD LSBUS clock frequency | 150 | 150 1 | 150 | 100 1 | 100 | MHz |
FFPD_TOPSW_CLK | Maximum FPD top-switch clock frequency | 1000 | 825 2 | 800 | 600 2 | 550 | MHz |
FDBG_FPD_CLK | Maximum debug FPD clock frequency | 400 | 400 3 | 400 | 400 3 | 333 | MHz |
|
Symbol | Description | Performance as a Function of Speed Grade and Operating Voltage (VCC_PSLP) | Units | ||||
---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||
-3 | -2 | -1 | -2 | -1 | |||
FRPLL_TO_XPD_CLK | Maximum RPU PLL to XPD clock frequency | 1200 | 1200 | 1200 | 1000 | 1000 | MHz |
FLPD_TOPSW_CLK | Maximum LPD top-switch clock frequency 1 | 750 | 600 2 | 600 | 450 2 | 400 | MHz |
FLPD_LSBUS_CLK | Maximum LPD LSBUS clock frequency 1 | 150 | 150 3 | 150 | 100 3 | 100 | MHz |
FIOP_SW_CLK | Maximum I/O peripherals (IOP) switch clock frequency | 250 | 250 | 250 | 250 | 250 | MHz |
FTS_REFCLK | Maximum time-stamp reference clock frequency | 100 | 100 | 100 | 100 | 100 | MHz |
FPSM_REFCLK | Maximum PS manager (PSM) reference clock frequency | 460 | 460 4 | 460 | 368 4 | 368 | MHz |
FDBG_LPD_CLK | Maximum debug LPD clock frequency | 400 | 400 5 | 400 | 400 5 | 333 | MHz |
FDBG_TS_CLK | Maximum debug time-stamp clock frequency | 400 | 400 6 | 400 | 400 6 | 333 | MHz |
FUSB_REFCLK | Maximum USB reference clock frequency | 60 | 60 | 60 | 60 | 60 | MHz |
FCPM5_TOPSW_CLK | Maximum CPM5 top-switch clock frequency | 1050 | 825 7 | 800 | 600 7 | 550 | MHz |
|
Symbol | Description | Performance as a Function of Speed Grade and Operating Voltage (VCC_PMC) | Units | ||||
---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||
-3 | -2 | -1 | -2 | -1 | |||
FPMC_IRO_CLK | PMC internal clock source typical frequency | 400 | 400 | 400 | 320 | 320 | MHz |
PMC internal clock source tolerance | +10/–17 | +10/–17 | +10/–17 | +10/–17 | +10/–17 | % |
Symbol | Description | Performance as a Function of Speed Grade and Operating Voltage (VCC_PMC) | Units | ||||
---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||
-3 | -2 | -1 | -2 | -1 | |||
FEFUSE_REFCLK | Maximum eFUSE reference clock frequency for reading | 115 | 115 | 115 | 92 | 92 | MHz |
Maximum eFUSE reference clock frequency for programming | 60 | 60 | 60 | 60 | 60 | MHz | |
FSMON_REFCLK | Maximum system monitor reference clock frequency | 300 | 300 | 300 | 300 | 300 | MHz |
FUSB_SREFCLK | Maximum USB suspend reference clock frequency | 115 | 115 | 115 | 92 | 92 | MHz |
FAXI_TO_REFCLK | Maximum AXI4 timeout reference clock frequency | 115 | 115 | 115 | 92 | 92 | MHz |
FCFU_REFCLK | Maximum configuration frame unit (CFU) reference clock frequency 1 | 400 | 400 | 400 | 320 | 320 | MHz |
Minimum CFU reference clock frequency | 20 | 20 | 20 | 20 | 20 | MHz | |
FLSBUS_REFCLK | Maximum PMC LSBUS reference clock frequency | 150 | 150 | 150 | 100 | 100 | MHz |
FNPI_REFCLK | Maximum NoC programming interface (NPI) reference clock frequency | 300 | 300 | 300 | 300 | 300 | MHz |
FHSM0_REFCLK | Maximum horizontal super module (HSM0) reference clock frequency used with HBM 2 | 200 | 200 | 200 | 200 | 200 | MHz |
FHSM1_REFCLK | Maximum horizontal super module (HSM1) reference clock frequency used with XPIO 3 | 200 | 200 | 200 | 200 | 200 | MHz |
FPL0_REFCLK | Maximum PL0 reference clock frequency | 400 | 350 | 350 | 300 | 250 | MHz |
FPL1_REFCLK | Maximum PL1 reference clock frequency | 400 | 350 | 350 | 300 | 250 | MHz |
FPL2_REFCLK | Maximum PL2 reference clock frequency | 400 | 350 | 350 | 300 | 250 | MHz |
FPL3_REFCLK | Maximum PL3 reference clock frequency | 400 | 350 | 350 | 300 | 250 | MHz |
FPPLL_TO_XPD_CLK | Maximum PMC PLL to XPD clock frequency | 1200 | 1200 | 1200 | 1000 | 1000 | MHz |
FNPLL_TO_XPD_CLK | Maximum NoC PLL to XPD clock frequency | 1200 | 1200 | 1200 | 1000 | 1000 | MHz |
|
Symbol | Description | Performance as a Function of Speed Grade and Operating Voltage (VCC_PMC) | Units | ||||
---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||
-3 | -2 | -1 | -2 | -1 | |||
FPMCPLL | PMC PLL output frequency | 2000 | 1800 | 1600 | 1300 | 1300 | MHz, Max |
270 | 270 | 270 | 270 | 270 | MHz, Min | ||
FPMCPLLVCO | PMC PLL VCO frequency | 4320 | 4320 | 4320 | 4320 | 4320 | MHz, Max |
2160 | 2160 | 2160 | 2160 | 2160 | MHz, Min | ||
TPMCPLLLOCK | PMC PLL lock time | 100 | 100 | 100 | 100 | 100 | μs, Max |
Symbol | Description | Performance as a Function of Speed Grade and Operating Voltage (VCC_PMC) | Units | ||||
---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||
-3 | -2 | -1 | -2 | -1 | |||
FNOCPLL | NoC PLL output frequency | 2000 | 1800 | 1600 | 1300 | 1300 | MHz, Max |
270 | 270 | 270 | 270 | 270 | MHz, Min | ||
FNOCPLLVCO | NoC PLL VCO frequency | 4320 | 4320 | 4320 | 4320 | 4320 | MHz, Max |
2160 | 2160 | 2160 | 2160 | 2160 | MHz, Min | ||
TNOCPLLLOCK | NoC PLL lock time | 100 | 100 | 100 | 100 | 100 | μs, Max |
Symbol | Description | Performance as a Function of Speed Grade and Operating Voltage (VCC_PSFP) | Units | ||||
---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||
-3 | -2 | -1 | -2 | -1 | |||
FPSAPLL | APU PLL output frequency | 2000 | 1800 | 1600 | 1300 | 1300 | MHz, Max |
270 | 270 | 270 | 270 | 270 | MHz, Min | ||
FPSAPLLVCO | APU PLL VCO frequency | 4320 | 4320 | 4320 | 4320 | 4320 | MHz, Max |
2160 | 2160 | 2160 | 2160 | 2160 | MHz, Min | ||
TPSAPLLLOCK | APU PLL lock time | 100 | 100 | 100 | 100 | 100 | μs, Max |
Symbol | Description | Performance as a Function of Speed Grade and Operating Voltage (VCC_PSLP) | Units | ||||
---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||
-3 | -2 | -1 | -2 | -1 | |||
FPSRPLL | RPU PLL output frequency | 2000 | 1800 | 1600 | 1300 | 1300 | MHz, Max |
270 | 270 | 270 | 270 | 270 | MHz, Min | ||
FPSRPLLVCO | RPU PLL VCO frequency | 4320 | 4320 | 4320 | 4320 | 4320 | MHz, Max |
2160 | 2160 | 2160 | 2160 | 2160 | MHz, Min | ||
TPSRPLLLOCK | RPU PLL lock time | 100 | 100 | 100 | 100 | 100 | μs, Max |
Symbol | Description | Performance as a Function of Speed Grade and Operating Voltage (VCC_CPM5) | Units | ||||
---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | |||||
-3 | -2 | -1 | -2 | -1 | |||
FCPM5PLL | CPM5 PLL output frequency | 1200 | 900 | 900 | 725 | 725 | MHz, Max |
270 | 270 | 270 | 270 | 270 | MHz, Min | ||
FCPM5PLLVCO | CPM5 PLL VCO frequency | 4320 | 4320 | 4320 | 4320 | 4320 | MHz, Max |
2160 | 2160 | 2160 | 2160 | 2160 | MHz, Min | ||
TCPM5PLLLOCK | CPM5 PLL lock time | 100 | 100 | 100 | 100 | 100 | μs, Max |