Reset Architecture

The CPM block receives a few reset inputs, as shown in the following figure. All are treated as asynchronous resets. The following figure shows the reset connectivity in the CPM.

Figure 1. CPM Reset Architecture

por_vccint_b is the main reset signal for the CPM block. This is driven by the PMC and is the same reset that is applied to the PL. por_vccint_b is only used by the CRCPM block in the CPM. It resets the PLL and clock divider and other related circuits in the CRCPM. All internal clocks in the CPM are active only after the de-assertion of por_vccint_b.

The CRCPM block includes reset registers to all sub-blocks in the CPM. By default all sub-blocks are held in reset. The PCSR interface between the PS-LPD and CPM contains the pcr_initstate signal that acts as the system reset for the CPM. This reset needs to be de-asserted before the CPM Interconnect can be accessed. After pcr_initstate is removed, the reset registers can then be configured by means of the CPM Interconnect to bring individual sub-blocks out of reset.

Table 1. CPM Resets
Reset name	Direction	Description
por_vccint_b	Input	Power on reset for CPM. Driven by PS/PMC.
if_ps_cpm_pcsr.pcr_initstate	Input	Serves as CPM system reset.
perst0	Input	Fundamental reset of PCIe controller. One per instance. Driven by IO inside PS.
perst1	Input
perst0_out	Output	Fundamental reset out from the PCIe controller. One per instance. This is simply a buffered output of perst0/1 and goes out to XPIPE.
perst1_out	Output

Note: The reset inputs are defined to be asynchronous, as PCIe defines PERST# as asynchronous. These resets can assert without notice asynchronously with transactions outstanding. This has the potential to cause orphaned transactions in CPM, PS, PMC, NOC, DDR etc. An optional firmware-based reset sequence is required to protect against this issue.