About CCIX

Versal ACAP CPM CCIX Architecture Manual (AM016)

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1.1 English

The Cache Coherent Interconnect for Accelerators (CCIX) is a chip-to-chip interconnect that enables two or more devices to share data in a cache-coherent manner. Machine learning and big data applications are fundamentally changing the way that data is processed. Classic processor data flows are now being augmented with off-chip accelerators that can be customized for specific types of applications, from compute accelerators to network traffic acceleration. This has driven an industry-wide movement towards accelerators and heterogeneous compute.

For many of today’s compute tasks, accelerators can complete the needed functionality both faster and with lower power consumption than the processor working on its own. However, unmanaged heterogeneity can bring software complexity. CCIX is poised to optimize and simplify how heterogeneous systems are designed while at the same time increasing bandwidth and reducing latency in the systems built with devices processing via processors with different instruction set architectures (ISAs), or application-specific accelerators. See the CCIX Consortium web page for more information.