The CPM PL Interface (CPI) interfaces with the accelerators in the PL on one
side using one CHI slave port. CPI interfaces with the L2 or CMN on the other side via
another CHI master port. The features of CPM PL Interface (CPI) are:
- Perform clock domain crossing of CHI port between CPM and PL.
- Perform up-sizing/downsizing of the data channels between 512-bit CHI interface on the PL side and 256-bit CHI interface on the L2 side.
- Perform credit management at L2 and PL interfaces in both directions independently.
- Track link states independently in both directions.
- Follow the link activation and deactivation sequences as described in the CHI specification.
- Support for L2 bypass feature.