CCIX Capable PCIe Controller

Versal ACAP CPM CCIX Architecture Manual (AM016)

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1.1 English

The Xilinx® Versal® ACAP CPM PCIe® block is a high-bandwidth, scalable, and reliable serial interconnect building block solution for use with Versal ACAP devices. Xilinx offers two PCIe controllers in the Versal CPM: the PCIe 0 controller, and the PCIe 1 controller. Both controllers are CCIX capable. The CPM PCIe block diagram is shown in the following figure.

Figure 1. CPM PCIe Block Diagram

The controllers in CCIX mode support EDR configurations at x4 and x8 widths and at speeds of 20 GT/s and 25 GT/s, as well as all other lower performance configurations: Gen1 (2.5 GT/s), Gen2 (5.0 GT/s), and Gen3 (8 GT/s). Only one controller supports Gen4 (16 GT/s). Both controllers are compliant to the CCIX Transport Specification 1.0.