AXI4-Stream Interconnect

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

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1.3 English

Each AI Engine tile has an AXI4-Stream interconnect (alternatively called a stream switch) that is a fully programmable, 32-bit, AXI4-Stream crossbar, and is statically configured through the memory-mapped AXI4 interconnect. It handles backpressure and is capable of the full bandwidth on the AXI4-Stream. The following figure is a high-level block diagram of the AXI4-Stream switch. The switch has master ports (data flowing from the switch) and slave ports (data flowing to the switch). The following figure shows an AXI4-Stream interconnect. The building blocks of the AXI4-Stream interconnect are listed as follows.

  • Port handlers
  • FIFOs
  • Arbiters
  • Stream switch configuration registers
Figure 1. AXI4-Stream Switch High-level Block Diagram

Each port has a port handler that selects the route for the input/output stream. Each master port and slave port contains buffering of a 4-deep FIFO with a two cycle latency. Each stream switch has two FIFO buffers (16-deep, 32-bit data + 1-bit TLAST wide) that can be chained together and used for adding buffering to a stream. Each switch has six programmable arbiters for packet switching.

Each stream port can be configured for either circuit-switched or packet-switched streams (never at the same time) using a packet-switching bit in the configuration register. A circuit-switched stream is a one-to-many streams. This means that it has exactly one source port and an arbitrary number of destination ports. All data entering the stream at the source is streamed to all destinations. A packet-switched stream can share ports (and therefore, physical wires) with other logical streams. Because there is a potential for resource contention with other packet-switched streams, they do not provide deterministic latency. The latency for the word transmitted in a circuit-switched stream is deterministic; if the bandwidth is limited, the built-in backpressure will cause performance degradation.

A packet-switched stream is identified by a 5-bit ID which has to be unique amongst all streams it shares ports with. The stream ID also identifies the destination of the packet. A destination can be an arbitrary number of master ports and packet-switched streams make it possible to realize all combinations of single/multiple master/slave ports in any given stream.

A packet-switched packet has:

Packet header
Routing and control information for the packet
Actual data in the packet
Last word in the packet must have TLAST asserted to mark the end of packet

The packet header is shown here:

Table 1. Packet Header
Odd Parity 3'b000 Source Column Source Row 1'b0 Packet Type 7'b0000000 Stream ID
[31] [30:28] [27:21] [20:16] [15] [14:12] [11:5] [4:0]

The following table summarizes the AXI4-Stream tile interconnect bandwidth for the -1L speed grade devices.

Table 2. AI Engine AXI4-Stream Tile Interconnect Bandwidth
Connection Type Number of Connections Data Width (bits) Clock Domain Bandwidth per Connection (GB/s) Aggregate Bandwidth (GB/s)
To North/From South 6 32 AI Engine (1 GHz) 4 24
To South/From North 4 32 AI Engine (1 GHz) 4 16
To West/From East 4 32 AI Engine (1 GHz) 4 16
To East/From West 4 32 AI Engine (1 GHz) 4 16