AI Engine Array Hierarchy

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

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1.3 English
The AI Engine array is made up of AI Engine tiles and AI Engine array interface tiles (the last row of the array). The types of interface tiles include the AI Engine to PL and AI Engine to NoC interface tiles. There is also exactly one configuration interface tile in each AI Engine array that contains a PLL for AI Engine clock generation and other global control functions. The following figure shows a conceptual view of the complete tile hierarchy associated with the AI Engine array. See AI Engine Tile Architecture and AI Engine Array Interface Architecture for detailed descriptions of the various tiles.
Figure 1. Hierarchy of Tiles in a AI Engine Array