The AI Engine configuration process writes a programmable device image (PDI) produced by the bootgen tool into AI Engine configuration registers. The AI Engine configuration is done over memory-mapped AXI4 via the NoC. Any master on the NoC can configure the AI Engine array. For more information on generating a PDI with the bootgen tool, refer to AI Engine Tools and Flows User Guide (UG1076).
The AI Engine array can be reconfigured at any time. The application drives the reconfiguration. Safe reconfiguration requires:
- Ensuring that reconfiguration is not occurring during ongoing traffic.
- Disabling the AI Engine to PL interface prior to reconfiguration.
- Draining all data in the sub-region before it is reconfigured to prevent side-effects from remnant data from a previous configuration.
- Complete reconfiguration
- The global reset is asserted for the AI Engine array and the entire array is reconfigured by downloading a new configuration image.
- Partial reconfiguration
- Some of the AI Engine tiles in the array are reconfigured while the rest of the tiles continue to run kernels. Reconfiguration occurs without affecting already running kernels in the AI Engine array.
The PMC and PS are responsible for initializing the AI Engine array. The following table summarizes the reset controls available for the global AI Engine array.
| Type | Trigger | Scope |
|---|---|---|
| Internal power-on-reset | Part of boot sequence | AI Engine array |
| System reset | NPI input | AI Engine array |
| INITSTATE reset | PCSR bit | AI Engine array |
| Array soft reset | Software register write over NPI | AI Engine array |
| AI Engine tile column reset | Memory-mapped AI Engine register bit in the array interface tile | AI Engine tile column |
| AI Engine array interface reset | From NPI register | AI Engine array interface tile |
The combination of column reset and array interface tile reset (refer to AI Engine Array Hierarchy) enables a partial reconfiguration use case where a sub-array that comprises AI Engine tiles and array interface tiles can be reset and reprogrammed without disturbing adjacent sub-arrays. The specifics of handling the array splitting and adding isolation depend on the type of use case (multi-user/tenancy or single-user/tenancy multiple-tasks).