AI Engine Array Overview

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

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1.3 English

The following figure shows the high-level block diagram of a Versal adaptive SoCs with an AI Engine array in it. The device consists of the processor system (PS), programmable logic (PL), and the AI Engine array.

Figure 1. Versal Device Top-Level Block Diagram

The AI Engine array is the top-level hierarchy of the AI Engine architecture. It integrates a two-dimensional array of AI Engine tiles. Each AI Engine tile integrates a very-long instruction word (VLIW) processor, integrated memory, and interconnects for streaming, configuration, and debug. The AI Engine array interface enables the AI Engine to communicate with the rest of the Versal device through the NoC or directly to the PL. The AI Engine array also interfaces to the processing system (PS) and platform management controller (PMC) through the NoC.