Interrupt Handling

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

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1.3 English

It is possible to setup interrupts to the processor system (PS) and the platform management controller (PMC) triggered by events inside the AI Engine array. This section gives an introduction to the types of interrupts from the AI Engine array.

The AI Engine array generates four interrupts that can be routed from the AI Engine array to the PMC, application processing unit (APU), and real-time processing unit (RPU). The overall hierarchy for interrupt generation from AI Engine array is as follows:

  • Events get triggered from any of the AI Engine tiles or AI Engine interface tiles.
  • Each column has first-level interrupt handlers that can capture the trigger/event generated and forward it to the second-level interrupt handler. Second-level interrupt handlers are only available in NoC interface tiles.
  • A second-level interrupt handler can drive any one of the four interrupt lines in a AI Engine array interface.
  • These four interrupt lines are eventually connected to the AI Engine configuration interface tile.

The following figure is a high-level block diagram showing the connections of the NPI interrupts from the AI Engine array to other blocks in the Versal device. The diagram does not show the actual layout/placement of the array interface tiles and the AI Engine tiles.

Figure 1. Connecting Interrupts from the AI Engine Array to Other Functional Blocks

In the previous figure, the four interrupts are generated from a NoC interface tile. They pass through the PL interface tile and reach a configuration interface tile. Internal errors (such as PLL lock loss) are then ORed with the four incoming interrupts and the resulting four interrupts are connected directly to the NPI interrupt signals on the NPI interface, which is a 32-bit wide memory-mapped AXI4 bus.

At the device level, the four NPI interrupts are assigned 4 to 7. There are three groups of NPI registers (IMR0…IMR3, IER0…IER3, and IDR0…IDR3). Each of the pairs (IMR, IER, and IDR) can be used to configure the four NPI interrupts. IMR registers are read only, and IER and IDR registers are write only. Only the registers corresponding to NPI interrupt 4 can be programmed. For NPI interrupts 5, 6, and 7, the three sets of registers have no effect and the three interrupts cannot be masked by programming the NPI register. The structure and address of the NPI registers are described in the Versal Adaptive SoC AI Engine Register Reference (AM015).