Array Interface Memory-Mapped AXI4 Interconnect

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

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1.3 English

The main task of the AI Engine memory-mapped AXI4 interconnect is to allow external access to internal AI Engine tile resources such as memories and registers for configuration and debug. It is not designed to carry the bulk of the data movement to and from the AI Engine array. The memory-mapped AXI4 interfaces are all interconnected across the AI Engine array interface row. This enables the memory-mapped AXI4 interconnects in the array interface tiles to move incoming memory-mapped signals to the correct column horizontally and then forward them vertically to the memory-mapped AXI4 interconnect in the bottom AI Engine tile of that column through a switch.

Each memory-mapped AXI4 interface is a 32-bit address with 32-bit data. The maximum memory-mapped AXI4 bandwidth is designed to be 1.5 GB/s.

To feed the memory-mapped AXI4 interface, the NoC module contains a memory-mapped AXI4 bridge that accepts memory-mapped AXI4 transfers from the NoC NSU interface, and acts as a memory-mapped AXI4 master to the internal memory-mapped AXI4 interface switch.