Version: Vitis 2024.2
Welcome to the Vitis Getting Started tutorial. The Vitis tool provides a unified flow for developing FPGA accelerated application targeted to either Data Center accelerator cards or Embedded Processor platforms. If you are looking to learn more about the Vitis application acceleration development flow in order to get started with FPGA acceleration, you have come to the right place.
This tutorial is divided into three separate flows:
These flows use the same host applications and accelerated kernel source code, but have differences in the build and implementation of the systems. Use the Embedded System design flow if you are working with an AMD Adaptive SoC device such as AMD Versal™, or Data Center Acceleration if you are working with an AMD Alveo™ accelerator card, and use the Vitis unified IDE flow if you are interested in working with the latest version of the Vitis tools.
This tutorial provides instructions for building and running on both the Alveo U250 Data Center accelerator card, and the AMD Zynq™ Ultrascale™ MPSoC ZCU102 platform. These instructions can be easily adapted to other AMD cards.
The two flows in this tutorial are both organized into five parts and are designed to walk you through all the key aspects of the Vitis flow.
Part 1 covers all the essential concepts of the Vitis FPGA acceleration flow in under 10 minutes.
Part 2 guides you through the process of installing the Vitis tools, platforms, and runtime library.
Part 3 explains the source code of vector-add example used in the rest of the tutorial.
Part 4 has three parts that describe the Embedded System flow and the Data Center acceleration flow as command line flows, and presents the new Vitis unified IDE. Each flow includes the commands required to compile, link, and run the example design.
Part 5 gives an overview of the Analysis view and shows how to open and analyze reports.